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FEATURES
Digitally Programmable Binary Gains from 1 to 16
Two-Chip Cascade Mode Achieves Binary Gain from
1 to 256
Gain Error:
0.01% Max, Gain = 1, 2, 4 (C Grade)
0.02% Max, Gain = 8, 16 (C Grade)
0.5 ppm/ C Drift Over Temperature
Fast Settling Time
10 V Signal Change:
0.01% in 4.5 s (Gain = 16)
Gain Change:
0.01% in 5.6 s (Gain = 16)
Low Nonlinearity: 0.005% FSR Max (J Grade)
Excellent DC Accuracy:
Offset Voltage: 0.5 mV Max (C Grade)
Offset Voltage Drift: 3 V/ C (C Grade)
TTL-Compatible Digital Inputs
PRODUCT DESCRIPTION
Software Programmable
Gain Amplifier
AD526
PIN CONFIGURATION
DIG GND
1
NULL
2
V
IN 3
NULL
4
16
A1
15
A0
14
CS
13
CLK
AD526
TOP VIEW
ANALOG GND 2
5
(Not to Scale)
12
A2
ANALOG GND 1
6
–V
S 7
V
OUT
SENSE
8
11
B
10
+V
S
9
V
OUT
FORCE
The AD526 is a single-ended, monolithic software program-
mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8
and 16. It is complete, including amplifier, resistor network
and TTL-compatible latched inputs, and requires no external
components.
Low gain error and low nonlinearity make the AD526 ideal for
precision instrumentation applications requiring programmable
gain. The small signal bandwidth is 350 kHz at a gain of 16. In
addition, the AD526 provides excellent dc precision. The FET-
input stage results in a low bias current of 50 pA. A guaranteed
maximum input offset voltage of 0.5 mV max (C grade) and low
gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using
Analog Devices’ laser trimming technology.
To provide flexibility to the system designer, the AD526 can be
operated in either latched or transparent mode. The force/sense
configuration preserves accuracy when the output is connected
to remote or low impedance loads.
The AD526 is offered in one commercial (0°C to +70°C) grade,
J, and three industrial grades, A, B and C, which are specified
from –40°C to +85°C. The S grade is specified from –55°C to
+125°C. The military version is available processed to MIL-
STD 883B, Rev C. The J grade is supplied in a 16-lead plastic
DIP, and the other grades are offered in a 16-lead hermetic
side-brazed ceramic DIP.
APPLICATION HIGHLIGHTS
1.
Dynamic Range Extension for ADC Systems:
A single
AD526 in conjunction with a 12-bit ADC can provide
96 dB of dynamic range for ADC systems.
2.
Gain Ranging Preamps:
The AD526 offers complete digital
gain control with precise gains in binary steps from 1 to 16.
Additional gains of 32, 64, 128 and 256 are possible by cas-
cading two AD526s.
ORDERING GUIDE
Model
AD526JN
AD526AD
AD526BD
AD526CD
AD526SD
AD526SD/883B
5962-9089401MEA*
Temperature
Range
Commercial
Industrial
Industrial
Industrial
Military
Military
Military
Package
Descriptions
16-Lead Plastic DIP
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
Package
Options
N-16
D-16
D-16
D-16
D-16
D-16
D-16
*Refer to official DESC drawing for tested specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD526–Typical Performance Characteristics
20
30
V
20
V
OUTPUT VOLTAGE SWING –
OUTPUT VOLTAGE SWING –
INPUT BIAS CURRENT – pA
15
+25 C
R
L
= 2k
10
15
V
IN
= 0
10
20
@ V
S
=
15V
10
5
5
0
0
5
10
SUPPLY VOLTAGE –
15
V
20
0
100
0
1k
LOAD RESISTANCE –
10k
0
5
10
SUPPLY VOLTAGE –
15
V
20
Figure 1. Output Voltage Swing vs.
Supply Voltage, G = 16
Figure 2. Output Voltage Swing vs.
Load Resistance
Figure 3. Input Bias Current vs.
Supply Voltage
100nA
75
20
10
16
8
10nA
INPUT BIAS CURRENT – pA
INPUT BIAS CURRENT
V
S
=
50
15V
4
GAIN
1nA
2
1
1
100pA
25
10pA
1pA
–60
–20
20
60
100
TEMPERATURE – C
140
0
–10
–5
0
5
INPUT VOLTAGE – V
10
10
100
1k
10k 100k
FREQUENCY – Hz
1M
10M
Figure 4. Input Bias Current vs.
Temperature
Figure 5. Input Bias Current vs. Input
Voltage
Figure 6. Gain vs. Frequency
25
FULL POWER RESPONSE – V p-p
POWER SUPPLY REJECTION – dB
100
1.0002
15V WITH 1V p-p
SINE WAVE
20
GAIN = 8, 16
80
+SUPPLY
60
15
GAIN = 1, 2, 4
NORMALIZED GAIN
1.0001
1.0000
10
40
–SUPPLY
20
0.9999
5
0
1k
10
10k
100k
1M
FREQUENCY – Hz
10M
1
10
100
1k
10k
FREQUENCY – Hz
100k
1M
0.9998
–60
–20
20
60
100
TEMPERATURE – C
140
Figure 7. Large Signal Frequency
Response
Figure 8. PSRR vs. Frequency
Figure 9. Normalized Gain vs.
Temperature, Gain = 1
–4–
REV. D
FPGA/CPLD
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