NXP Semiconductors
Data Sheet: Advance Information
Document Number S32K1XX
Rev. 7, 04/2018
S32K1xx Data Sheet
Notes
• Technical information for the S32K116 and S32K118
device families is preliminary until these devices
achieve qualification.
• Following two are the available attachments with
Datasheet:
– S32K1xx_Orderable_Part_Number_ List.xlsx
– S32K1xx_Power_Modes_Configuration.xlsx
Key Features
• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for
HSRUN mode, -40 °C to 125 °C for RUN mode
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU
– Supports up to 112 MHz frequency (HSRUN mode)
with 1.25 Dhrystone MIPS per MHz
– Arm Core based on the Armv7 Architecture and
Thumb®-2 ISA
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller
(NVIC)
– Single Precision Floating Point Unit (FPU)
• Clock interfaces
– 4 - 40 MHz fast external oscillator (SOSC)
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz (HSRUN) System Phased Lock
Loop (SPLL)
– Up to 50 MHz DC external square wave input clock
– Real Time Counter (RTC)
S32K1XX
• Power management
– Low-power Arm Cortex-M4F/M0+ core with
excellent energy efficiency
– Power Management Controller (PMC) with multiple
power modes: HSRUN, RUN, STOP, VLPR, and
VLPS. Note: CSEc (Security) or EEPROM writes/
erase will trigger error flags in HSRUN mode (112
MHz) because this use case is not allowed to
execute simultaneously. The device will need to
switch to RUN mode (80 Mhz) to execute CSEc
(Security) or EEPROM writes/erase.
– Clock gating and low power operation supported on
specific peripherals.
• Memory and memory interfaces
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC
and EEPROM emulation. Note: CSEc (Security) or
EEPROM writes/erase will trigger error flags in
HSRUN mode (112 MHz) because this use case is
not allowed to execute simultaneously. The device
will need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
– Up to 256 KB SRAM with ECC
– Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
– Up to 4 KB Code cache to minimize performance
impact of memory access latencies
– QuadSPI with HyperBus™ support
• Mixed-signal analog
– Up to two 12-bit Analog-to-Digital Converter
(ADC) with up to 32 channel analog inputs per
module
– One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
• Debug functionality
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
– Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI)
– Up to 156 GPIO pins with interrupt functionality
– Non-Maskable Interrupt (NMI)
This document contains information on a pre-production product. Specifications
and pre-production information herein are subject to change without notice.
• Communications interfaces
– Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support
and low power availability
– Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
– Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
– Up to three FlexCAN modules (with optional CAN-FD support)
– FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).
– Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules.
• Safety and Security
– Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the
SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will
trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The
device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
– 128-bit Unique Identification (ID) number
– Error-Correcting Code (ECC) on flash and SRAM memories
– System Memory Protection Unit (System MPU)
– Cyclic Redundancy Check (CRC) module
– Internal watchdog (WDOG)
– External Watchdog monitor (EWM) module
• Timing and control
– Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)
– One 16-bit Low Power Timer (LPTMR) with flexible wake up control
– Two Programmable Delay Blocks (PDB) with flexible trigger system
– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
– 32-bit Real Time Counter (RTC)
• Package
– 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP package
options
• 16 channel DMA with up to 63 request sources using DMAMUX
S32K1xx Data Sheet, Rev. 7, 04/2018
2
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 4
Feature comparison............................................................................ 5
Ordering information......................................................................... 7
3.1 Selecting orderable part number ...............................................7
3.2 Ordering information ................................................................ 8
4
General............................................................................................... 9
4.1 Absolute maximum ratings........................................................9
4.2 Voltage and current operating requirements..............................10
4.3 Thermal operating characteristics..............................................11
4.4 Power and ground pins.............................................................. 12
4.5 LVR, LVD and POR operating requirements............................14
4.6 Power mode transition operating behaviors.............................. 15
4.7 Power consumption................................................................... 16
4.8 ESD handling ratings.................................................................20
4.9 EMC radiated emissions operating behaviors........................... 20
5
I/O parameters....................................................................................21
5.1 AC electrical characteristics...................................................... 21
5.2 General AC specifications......................................................... 21
5.3 DC electrical specifications at 3.3 V Range.............................. 22
5.4 DC electrical specifications at 5.0 V Range.............................. 23
5.5 AC electrical specifications at 3.3 V range .............................. 24
5.6 AC electrical specifications at 5 V range ................................. 24
5.7 Standard input pin capacitance.................................................. 25
5.8 Device clock specifications....................................................... 25
6
Peripheral operating requirements and behaviors.............................. 26
6.1 System modules......................................................................... 26
6.2 Clock interface modules............................................................ 26
6.2.1
6.2.2
6.2.3
External System Oscillator electrical specifications....26
External System Oscillator frequency specifications . 28
System Clock Generation (SCG) specifications.......... 30
6.2.3.1
Fast internal RC Oscillator (FIRC)
electrical specifications............................ 30
6.2.3.2
Slow internal RC oscillator (SIRC)
electrical specifications ........................... 30
6.2.4
Low Power Oscillator (LPO) electrical specifications
......................................................................................31
9
8
7
6.4.2
6.3.2
6.3.1.2
6.2.5
SPLL electrical specifications .....................................31
6.3 Memory and memory interfaces................................................31
6.3.1
Flash memory module (FTFC) electrical
specifications................................................................31
6.3.1.1
Flash timing specifications —
commands................................................ 31
Reliability specifications..........................36
QuadSPI AC specifications..........................................37
6.4 Analog modules......................................................................... 41
6.4.1
ADC electrical specifications...................................... 41
6.4.1.1
6.4.1.2
12-bit ADC operating conditions............. 41
12-bit ADC electrical characteristics....... 43
CMP with 8-bit DAC electrical specifications............ 45
6.5 Communication modules........................................................... 49
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
LPUART electrical specifications............................... 49
LPSPI electrical specifications.................................... 49
LPI2C electrical specifications.................................... 55
FlexCAN electical specifications.................................56
SAI electrical specifications........................................ 56
Ethernet AC specifications.......................................... 58
Clockout frequency......................................................61
6.6 Debug modules.......................................................................... 61
6.6.1
6.6.2
6.6.3
SWD electrical specofications .................................... 61
Trace electrical specifications......................................63
JTAG electrical specifications..................................... 64
Thermal attributes.............................................................................. 67
7.1 Description.................................................................................67
7.2 Thermal characteristics..............................................................67
7.3 General notes for specifications at maximum junction
temperature................................................................................ 72
Dimensions.........................................................................................73
8.1 Obtaining package dimensions ................................................. 73
Pinouts................................................................................................74
9.1 Package pinouts and signal descriptions....................................74
10 Revision History.................................................................................74
S32K1xx Data Sheet, Rev. 7, 04/2018
NXP Semiconductors
3
Block diagram
1 Block diagram
Following figures show superset high level architecture block diagrams of S32K14x
series and S32K11x series respectively. Other devices within the family have a subset of
the features. See
Feature comparison
for chip specific values.
Async
Trace
port
JTAG &
Serial Wire
MCM
TPIU
SWJ-DP
Arm Cortex M4F
Core
PPB
NVIC
ITM
FPU
DSP
DCODE
ICODE
AWIC
AHB-AP
FPB
DWT
System
Clock generation
DMA
MUX
LPO
128 kHz
SIRC
8 MHz
FIRC
48 MHz
SOSC
4-40 MHz 8-40 MHz
Mux
System MPU
1
LMEM
Main SRAM
2
Upper region
Lower region
eDMA
TCD
512B
SPLL
EIM
LMEM
controller
Code Cache
ENET
S1
M0
S2
M1
M2
M3
S3
S0
Crossbar switch (AXBS-Lite)
System MPU
1
Mux
GPIO
System MPU
1
QuadSPI
System MPU
1
Flash memory
controller
FlexRAM/
SRAM
Peripheral bus controller
Low Power
Timer
QSPI
ERM
WDOG
CMP
8-bit DAC
12-bit ADC
LPI2C
FlexIO
LPIT
Code flash
memory
Data flash
memory
CSEc
3
EWM
LPUART
FlexCAN
FlexTimer
CRC
TRGMUX
LPSPI
PDB
LPIT
RTC
SAI
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned
different access rights to each protected memory region. The Arm M4 core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this
use case is not allowed to execute simultaneously. The device need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
Device architectural IP
on all S32K devices
Key:
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section)
Figure 1. High-level architecture diagram for the S32K14x family
S32K1xx Data Sheet, Rev. 7, 04/2018
4
NXP Semiconductors
Feature comparison
IO PORT
Arm Cortex M0+
IO PORT
Clock generation
LPO
128 kHz
Serial Wire
SW-DP
AHB-AP
NVIC
PPB
BPU
MTB+DWT
AWIC
DMA
MUX
SIRC
8 MHz
FIRC
48 MHz
SOSC
4-40 MHz
M0
System MPU
1
Flash memory
controller
FlexRAM/
SRAM
2
Unified Bus
AHBLite
S0
eDMA
M2
AHBLite
Crossbar switch (AXBS-Lite)
S1
S2
System MPU
1
EIM
SRAM
2
Code flash
memory
Data flash
memory
ERM
CSEc
CMU
CMP
8-bit DAC
Peripheral bus controller
WDOG
12-bit ADC
LPI2C
FlexIO
Low Power
Timer
LPIT
LPUART
FlexCAN
FlexTimer
GPIO
CRC
TRGMUX
LPSPI
PDB
RTC
LPIT
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The Arm M0+ core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
Device architectural IP
on all S32K devices
Key:
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section)
Figure 2. High-level architecture diagram for the S32K11x family
2 Feature comparison
The following figure summarizes the memory, peripherals and packaging options for the
S32K1xx devices. All devices which share a common package are pin-to-pin compatible.
S32K1xx Data Sheet, Rev. 7, 04/2018
NXP Semiconductors
5
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