530QB682M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530QB682M000DGR

530QB682M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 682MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530QB682M000DGR Overview

CMOS/TTL Output Clock Oscillator, 682MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530QB682M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	682 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

LB1405, 15-level display circuit application (c)

Delay lamp circuit using power switch integrated circuit (2)

MC145026 (general) infrared, ultrasonic or radio frequency remote control transmission encoding circuit-02

Battery low voltage detector circuit diagram

Astable circuits with amplitude stability

Computer motherboard circuit diagram 815 5_05

Printer development: Does anyone know how to develop software for a printer? I mean the control program for the printer itself, not the PC version?...; 5151515151 Embedded System

About CAN communication rate setting: one, CAN clock cycle (Tq) = 2*crystal clock*BRP (baudrate prescaler) A CAN time is called a time quantum Tq 1) Synchronization Segment: 1 Tq, tSS 2) Propagation Segment: The propagation segment durati...; Aguilera Microcontroller MCU

Analysis of power management chip mc13892: The I.MX5x series uses Freescale's MC13892 as a PMIC. The schematic diagram pasted here takes the I.MX51 EVK board as an example.Features? Battery charger system for wall charging and USB charging ? 1...; kaola22 Power technology

Please give me some advice on TFT display, thank you!: :) Urgent help! Experts please give me some advice! ! ! ! :) I want to ask, using ATmega128 as the main control chip, TFT liquid crystal display, and DS1302 to make a perpetual calendar. First, LCD160...; bianyuan2010 Microchip MCU

Embedded MCU Model: Question 1: What version of Linux is used in the company when developing embedded systems? Is it Red Hat (this is the one in the video)? What is the kernel? Question 2: What is the model of MCU? You w...; yiran Embedded System

Ask a question about address decoding for communication between DSP and FPGA: The DSP data bus and address bus are both connected to the FPGA. The FPGA has multiple functional modules and needs to communicate with the DSP in multiple ways, that is, different numbers are obtaine...; luoyuanhong2008 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components