HY27US16561A-FPCS datasheet, PDF

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HY27US16561A-FPCS: DescriptionFlash, 16MX16, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, FBGA-63; Categorystorage storage; File Size423KB，47 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HY27US16561A-FPCS Overview

Flash, 16MX16, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, FBGA-63

HY27US16561A-FPCS Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	VFBGA, BGA63,10X12,32
Contacts	63
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	30 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
JESD-609 code	e1
length	11 mm
memory density	268435456 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	2K
Number of terminals	63
word count	16777216 words
character code	16000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA63,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
page size	256 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Programming voltage	3.3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	8K
Maximum standby current	0.00005 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
switch bit	NO
type	SLC NAND TYPE
width	9 mm

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HY27US(08/16)561A Series

HY27SS(08/16)561A Series

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash

Document Title

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory

Revision History

Revision

No.

0.0

Initial Draft.

1) Change AC Parameter

tCRY(1.8V)

Before

50+tr(R/B#)

60+tr(R/B#)

History

Draft Date

Apr. 04. 2005

Remark

Preliminary

0.1

After

Jul. 07. 2005

Preliminary

2) Change 256Mb Package Type.

- WSOP package is changed to USOP package.

- Figure & dimension are changed.

Correct the test Conditions (DC Characteristics table)

Test Conditions (

CC1)

Before

Test Conditions (

LI,

)

VIN=VOUT=0 to 3.6V

=50ns,

CE#=

OUT

=0mA

(1.8V=60ns,

3.3V=50ns)

CE#=

OUT

=0mA

After

VIN=VOUT=0 to Vcc (max)

0.2

Change AC Conditions table

Add tWW parameter ( tWW = 100ns, min)

- Texts & Figures are added.

- tWW is added in AC timing characteristics table.

4) Edit Copy Back Program operation step

5) Edit System Interface Using CE don’t care Figures.

6) Correct Address Cycle Map.

7) Change NOP (table 11)

Main Array

Before

After

Aug. 08. 2005

Preliminary

Spare Array

Rev 0.5 / Jun. 2006

HY27US(08/16)561A Series

HY27SS(08/16)561A Series

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27(U/S)S(08/16)561A series is a 32Mx8bit with spare 8Mx16 bit capacity. The device is offered in 1.8V

Vcc Power Supply and in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 2048 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected

Flash cells.

A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in

typical 2ms on a 16K-byte(X8 device) block.

Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP input pin.

The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-

ple memories the R/B pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)561A extended reliability of 100K pro-

gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

The chip could be offered with the CE don’t care function. This function allows the direct download of the code from

the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,

Read ID2 extension.

The Hynix HY27(U/S)S(08/16)561A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm,

FBGA 9 x 11 mm.

1.1 Product List

PART NUMBER

HY27SS08561A

HY27SS16561A

HY27US08561A

HY27US16561A

ORIZATION

x16

VCC RANGE

1.70 - 1.95 Volt

63FBGA / 48TSOP1 / 48USOP1

2.7V - 3.6 Volt

PACKAGE

Rev 0.5 / Jun. 2006

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