HD6432138WXXXFA datasheet, PDF - EEWORLD Datasheet

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HD6432138WXXXFA: DescriptionMicrocontroller, 16-Bit, MROM, H8S/2000 CPU, 20MHz, CMOS, PQFP80, PLASTIC, QFP-80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，891 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD6432138WXXXFA Overview

Microcontroller, 16-Bit, MROM, H8S/2000 CPU, 20MHz, CMOS, PQFP80, PLASTIC, QFP-80

HD6432138WXXXFA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	QFP, QFP80,.7SQ
Contacts	80
Reach Compliance Code	unknown
Has ADC	YES
Address bus width	16
bit size	16
CPU series	H8S/2000
maximum clock frequency	20 MHz
DAC channel	YES
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQFP-G80
JESD-609 code	e0
length	14 mm
Number of I/O lines	66
Number of terminals	80
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP80,.7SQ
Package shape	SQUARE
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	4096
rom(word)	32768
ROM programmability	MROM
Maximum seat height	3.05 mm
speed	20 MHz
Maximum slew rate	120 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Hitachi Single-Chip Microcomputer

H8S/2138 Series

H8S/2134 Series

H8S/2138F-ZTAT™

H8S/2134F-ZTAT™

H8S/2138 HD6432138W, HD6432138, HD64F2138,

HD64F2138V H8S/2137 HD6432137W, HD6432137

H8S/2134 HD6432134, HD64F2134, HD64F2134V

H8S/2133 HD6432133

H8S/2132 HD6432132, HD64F2132R, HD64F2132V

H8S/2130 HD6432130

Hardware Manual

ADE-602-144A

Rev. 2.0

3/12/99

©

Hitachi, Ltd. 1997

Contents

Contents ..... .....................................................................................................i

Preface ....... .....................................................................................................1

Section 1 Overview ........................................................................................3

1.1 Overview ......................................................................................................................... 3

1.2 Internal Block Diagram.................................................................................................... 8

1.3 Pin Arrangement and Functions ....................................................................................... 10

1.3.1 Pin Arrangement................................................................................................. 10

1.3.2 Pin Functions in Each Operating Mode ............................................................... 12

1.3.3 Pin Functions ...................................................................................................... 19

Section 2 CPU................................................................................................25

2.1 Overview ......................................................................................................................... 25

2.1.1 Features .............................................................................................................. 25

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ................................... 26

2.1.3 Differences from H8/300 CPU ............................................................................ 27

2.1.4 Differences from H8/300H CPU ......................................................................... 27

2.2 CPU Operating Modes ..................................................................................................... 28

2.3 Address Space.................................................................................................................. 33

2.4 Register Configuration ..................................................................................................... 34

2.4.1 Overview ............................................................................................................ 34

2.4.2 General Registers................................................................................................ 35

2.4.3 Control Registers ................................................................................................ 36

2.4.4 Initial Register Values ........................................................................................ 37

2.5 Data Formats.................................................................................................................... 38

2.5.1 General Register Data Formats ........................................................................... 38

2.5.2 Memory Data Formats ........................................................................................ 40

2.6 Instruction Set.................................................................................................................. 41

2.6.1 Overview ............................................................................................................ 41

2.6.2 Instructions and Addressing Modes..................................................................... 42

2.6.3 Table of Instructions Classified by Function ....................................................... 44

2.6.4 Basic Instruction Formats ................................................................................... 54

2.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... 55

2.7 Addressing Modes and Effective Address Calculation...................................................... 55

2.7.1 Addressing Mode................................................................................................ 55

2.7.2 Effective Address Calculation............................................................................. 59

i

2.8 Processing States.............................................................................................................. 62

2.8.1 Overview ............................................................................................................ 62

2.8.2 Reset State.......................................................................................................... 64

2.8.3 Exception-Handling State ................................................................................... 64

2.8.4 Program Execution State..................................................................................... 65

2.8.5 Bus-Released State ............................................................................................. 66

2.8.6 Power-Down State .............................................................................................. 66

2.9 Basic Timing ................................................................................................................... 67

2.9.1 Overview ............................................................................................................ 67

2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 67

2.9.3 On-Chip Supporting Module Access Timing....................................................... 69

2.9.4 External Address Space Access Timing .............................................................. 70

Section 3 MCU Operating Modes .................................................................. 71

3.1 Overview ......................................................................................................................... 71

3.1.1 Operating Mode Selection .................................................................................. 71

3.1.2 Register Configuration........................................................................................ 72

3.2 Register Descriptions ....................................................................................................... 72

3.2.1 Mode Control Register (MDCR)......................................................................... 72

3.2.2 System Control Register (SYSCR)...................................................................... 73

3.2.3 Bus Control Register (BCR) ............................................................................... 75

3.2.4 Serial Timer Control Register (STCR) ................................................................ 76

3.3 Operating Mode Descriptions........................................................................................... 77

3.3.1 Mode 1 ............................................................................................................... 77

3.3.2 Mode 2 ............................................................................................................... 77

3.3.3 Mode 3 ............................................................................................................... 78

3.4 Pin Functions in Each Operating Mode ............................................................................ 78

3.5 Memory Map in Each Operating Mode ............................................................................ 79

Section 4 Exception Handling ........................................................................ 89

4.1 Overview ......................................................................................................................... 89

4.1.1 Exception Handling Types and Priority............................................................... 89

4.1.2 Exception Handling Operation............................................................................ 90

4.1.3 Exception Sources and Vector Table................................................................... 90

4.2 Reset................................................................................................................................ 92

4.2.1 Overview ............................................................................................................ 92

4.2.2 Reset Sequence................................................................................................... 92

4.2.3 Interrupts after Reset........................................................................................... 94

4.3 Interrupts ......................................................................................................................... 95

4.4 Trap Instruction ............................................................................................................... 96

4.5 Stack Status after Exception Handling ............................................................................. 97

4.6 Notes on Use of the Stack ................................................................................................ 98

ii

Section 5 Interrupt Controller.........................................................................99

5.1 Overview ......................................................................................................................... 99

5.1.1 Features .............................................................................................................. 99

5.1.2 Block Diagram.................................................................................................... 100

5.1.3 Pin Configuration................................................................................................ 101

5.1.4 Register Configuration........................................................................................ 101

5.2 Register Descriptions ....................................................................................................... 102

5.2.1 System Control Register (SYSCR)...................................................................... 102

5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 103

5.2.3 IRQ Enable Register (IER) ................................................................................. 104

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 105

5.2.5 IRQ Status Register (ISR) ................................................................................... 106

5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) .......................................... 107

5.2.7 Address Break Control Register (ABRKCR)....................................................... 108

5.2.8 Break Address Registers A, B, C (BARA, BARB, BARC).................................. 109

5.3 Interrupt Sources.............................................................................................................. 110

5.3.1 External Interrupts .............................................................................................. 110

5.3.2 Internal Interrupts ............................................................................................... 112

5.3.3 Interrupt Exception Vector Table........................................................................ 112

5.4 Address Breaks ................................................................................................................ 115

5.4.1 Features .............................................................................................................. 115

5.4.2 Block Diagram.................................................................................................... 115

5.4.3 Operation............................................................................................................ 116

5.4.4 Usage Notes........................................................................................................ 116

5.5 Interrupt Operation........................................................................................................... 118

5.5.1 Interrupt Control Modes and Interrupt Operation ................................................ 118

5.5.2 Interrupt Control Mode 0 .................................................................................... 121

5.5.3 Interrupt Control Mode 1 .................................................................................... 123

5.5.4 Interrupt Exception Handling Sequence .............................................................. 126

5.5.5 Interrupt Response Times ................................................................................... 127

5.6 Usage Notes..................................................................................................................... 128

5.6.1 Contention between Interrupt Generation and Disabling ..................................... 128

5.6.2 Instructions that Disable Interrupts...................................................................... 129

5.6.3 Interrupts during Execution of EEPMOV Instruction .......................................... 129

5.7 DTC Activation by Interrupt ............................................................................................ 130

5.7.1 Overview ............................................................................................................ 130

5.7.2 Block Diagram.................................................................................................... 130

5.7.3 Operation............................................................................................................ 131

iii

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