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K4F170412D-BL50

Description
Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24
Categorystorage    storage   
File Size225KB,20 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K4F170412D-BL50 Overview

Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24

K4F170412D-BL50 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
Parts packaging codeSOJ
package instructionSOJ, SOJ24/26,.34
Contacts24
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFAST PAGE
Maximum access time50 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
I/O typeCOMMON
JESD-30 codeR-PDSO-J24
JESD-609 codee0
length17.15 mm
memory density16777216 bit
Memory IC TypeFAST PAGE DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals24
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ24/26,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height3.76 mm
self refreshYES
Maximum standby current0.0002 A
Maximum slew rate0.09 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
K4F170411D, K4F160411D
K4F170412D, K4F160412D
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 4Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for high level computer, microcomputer and personal computer.
FEATURES
• Part Identification
- K4F170411D-B(F) (5V, 4K Ref.)
- K4F160411D-B(F) (5V, 2K Ref.)
- K4F170412D-B(F) (3.3V, 4K Ref.)
- K4F160412D-B(F) (3.3V, 2K Ref.)
Active Power Dissipation
Unit : mW
Speed
4K
-50
-60
324
288
3.3V
2K
396
360
4K
495
440
5V
2K
605
550
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
Refresh Cycles
Part
NO.
K4F170411D
K4F170412D
K4F160411D
K4F160412D
V
CC
5V
3.3V
5V
3.3V
2K
32ms
Refresh
cycle
4K
Refresh period
Normal
64ms
128ms
L-ver
RAS
CAS
W
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
VBB Generator
Data in
Refresh Timer
Refresh Control
Refresh Counter
Memory Array
4,194,304 x 4
Cells
Row Decoder
Sense Amps & I/O
Buffer
Performance Range
Speed
-50
-60
DQ0
to
DQ3
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
A0-A11
(A0 - A10)
*1
A0 - A9
(A0 - A10)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Data out
Buffer
OE
Note)
*1
: 2K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
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