75185-S20-R datasheet, PDF - EEWORLD Datasheet

75185-S20-R: DescriptionMULTIPLE RS-232 DRIVERS AND RECEIVERS; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size30KB，2 Pages; ManufacturerUNISONIC TECHNOLOGIES CO.,LTD; Websitehttp://www.unisonic.com.tw/

Download Datasheet Parametric View All

75185-S20-R Overview

MULTIPLE RS-232 DRIVERS AND RECEIVERS

Parameter Name	Attribute value
Maker	UNISONIC TECHNOLOGIES CO.,LTD
Parts packaging code	SOIC
package instruction	SOP,
Contacts	20
Reach Compliance Code	compliant
ECCN code	EAR99
Differential output	NO
Number of drives	3
Input properties	SCHMITT TRIGGER
Interface integrated circuit type	LINE TRANSCEIVER
Interface standards	V.10; V.11; V.28; EIA-232-F; TIA-232-F; EIA-422-B; TIA-422-B; EIA-423-B; TIA-423-B
JESD-30 code	R-PDSO-G20
length	12.7 mm
Nominal negative supply voltage	-9 V
Number of functions	3
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Maximum receive delay	500 ns
Number of receiver bits	5
Maximum seat height	2.85 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
Supply voltage 1-max	15 V
Mains voltage 1-minute	7.5 V
Supply voltage1-Nom	9 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
maximum transmission delay	500 ns
width	7.65 mm
Base Number Matches	1

6701 Compilation Problem: I wrote 6701 today, and the CMD file is as follows: -c -heap 0x1000 -stack 0x1000 MEMORY { VECS: o = 00000000h l = 00000200h BOOTRAM: o = 00000200h l = 00000200h PMEM: o = 00010000h l = 0000FC00h DMEM...; coldsun1982 DSP and ARM Processors

Universal serial port VHDL source program design: Part 1: Serial port receiving program LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; --LIBRARY ALTERA;--USE ALTERA.MAXPLUS2.ALL; LIBRARY LPM;USE...; eeleader FPGA/CPLD

I will be interviewing at Baidu next week. Please give me some advice, education, corrections, help and concern.: [i=s] This post was last edited by astwyg on 2014-5-22 21:29 [/i] I was helping a classmate pass on the news and applied for an internship in Baidu's quality department. Unexpectedly, I received a cal...; astwyg Talking

Help: FPGA and DSP communication problem: FPGA uses DSP's xintf interface to communicate with DSP. I have read a lot of information, but I am still confused. How can I make the timing of FPGA consistent with DSP? I have seen people say that d...; djky183 FPGA/CPLD

Show the WEBENCH design process + low-pass filter design solution: Previously, I knew that WEBENCH design was for power supply design. Now I see that its functions are much more powerful. Now I will use this tool to design a low-pass filter circuit. The circuit diagr...; hanskying666 Analogue and Mixed Signal

Questions about AP1501: When testing, the input voltage of the component is 13.77V, and the output voltage is 4.99V. Then I added a multimeter in front of the component to measure the input current. At this time, the input v...; ena Power technology

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components