WM2613 datasheet, PDF - EEWORLD Datasheet

WM2613

Byte-wide Parallel Input, 12-bit Voltage Output DAC

Production Data, June 1999, Rev 1.0

FEATURES

•

Dual 12-bit voltage output DAC

Dual supply 2.7V to 5.5V operation

DNL

±

0.4 LSB, INL

±

1.5 LSB

Programmable settling time 1µ s or 3µ s typical

µ

8-bit micro controller compatible interface

Power down mode (10nA)

DESCRIPTION

The WM2613 is a 12-bit voltage output, resistor string, digital-to-

analogue converter. The DAC can be powered down under

software or hardware control, reducing power consumption to

10nA.

The device has an 8-bit microcontroller compatible parallel

interface. The eight data LSBs, the four data MSBs, and the three

control bits are written using three different addresses.

Excellent performance is delivered with a typical DNL of 0.4 LSBs.

The output stage is buffered by a x2 gain near rail-to-rail amplifier,

which features a Class A output stage (slow mode, class AB). The

settling time of the DAC is software programmable to allow the

designer to optimize speed versus power dissipation.

The device is available in a 20-pin TSSOP package. Commercial

temperature (0° to 70°C) and Industrial temperature (-40° to 85°C)

variants are supported.

APPLICATIONS

•

Battery powered test instruments

Digital offset and gain adjustment

Battery operated/remote industrial controls

Machine and motion control devices

Wireless telephone and communication systems

Speech synthesis

Arbitrary waveform generation

ORDERING INFORMATION

DEVICE

WM2613CDT

WM2613IDT

TEMP. RANGE

0° to 70°C

-40° to 85°C

PACKAGE

20-pin TSSOP

BLOCK DIAGRAM

DVDD

(10)

REFIN(12)

SPD (9)

NPD (15)

POWERDOWN/

SPEED

CONTROL

REFERENCE

INPUT BUFFER

X1

AVDD

(11)

TYPICAL PERFORMANCE

1

AVDD = DVDD = 5V, V

REF

= 2.048V, Speed = Fast mode, Load = 10k/100pF

0.8

0.6

0.4

DNL - LSB

(13) OUT

A[0-1] (8,7)

PARALLEL

INTERFACE

AND

CONTROL

LOGIC

3-BIT

CONTROL

LATCH

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

0

512

1024

1536

2048

DIGITAL CODE

2559

3071

3583

4095

DAC

OUTPUT

BUFFER

12-BIT DAC

LATCH

X2

NCS (18)

NWE (17)

4-BIT DAC

MSW

HOLDING

LATCH

8-BIT DAC

LSW

HOLDING

LATCH

D[0-7]

(19,20, 1-6)

POWER-ON

RESET

(14)

GND

(16)

NLDAC

WM2613

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK

Tel: +44 (0) 131 667 9386

Fax: +44 (0) 131 667 5176

Email: sales@wolfson.co.uk

http://www.wolfson.co.uk

Production Data

Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson

Microelectronics’ Terms and conditions.

Master rev 1.0.doc June 17, 1999 14:12

Wolfson Microelectronics Ltd

.

WM2613

PIN CONFIGURATION

D2

D3

D4

D5

D6

D7

A1

A0

SPD

DVDD

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

D1

D0

NCS

NWE

NLDAC

NPD

GND

OUT

REFIN

AVDD

Production Data Rev 1.0

PIN DESCRIPTION

PIN NO

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

NAME

D2

D3

D4

D5

D6

D7

A1

A0

SPD

DVDD

AVDD

REFIN

OUT

GND

NPD

NLDAC

NWE

NCS

D0

D1

TYPE

Digital input

Supply

Analogue input

Analogue output

Supply

Digital input

Data input.

Address input.

Speed select. Digital input.

Digital positive power supply.

Analogue positive power supply.

Voltage reference input.

DAC analogue voltage output.

Ground.

Power down. Active low digital input which powers down all analogue

circuits.

Load DAC. Digital input active low. NLDAC must be taken low to update

the DAC latch from the holding latches.

Write enable. Digital input active low.

Chip select. Digital input active low.

Data input.

DESCRIPTION

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June 1999

2

Production Data

WM2613

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or

beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to

damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this

device.

CONDITION

Supply voltages, AVDD or DVDD to GND

Supply voltage differences, AVDD to DVDD

Reference input voltage

Digital input voltage range to GND

Operating temperature range, T

A

Storage temperature

Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

WM2613C

WM2613I

-2.8V

-0.3V

0°C

-40°C

-65°C

MIN

MAX

7V

2.8V

DVDD + 0.3V

AVDD + 0.3V

70°C

85°C

150°C

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Supply voltage

High-level digital input voltage

Low-level digital input voltage

Reference voltage to REFIN

Load resistance

Load capacitance

Operating free-air temperature

SYMBOL

AVDD, DVDD

V

IH

V

IL

V

REF

R

L

C

L

T

A

WM2613CDT

WM2613IDT

Note: Reference voltages greater than AVDD/2 will cause saturation for large DAC codes.

0

-40

DVDD = 2.7V to 5.5V

See Note

2

100

70

85

TEST CONDITIONS

MIN

2.7

2

0.8

AVDD - 1.5

TYP

MAX

5.5

UNIT

V

kΩ

pF

°C

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June 1999

3

WM2613

ELECTRICAL CHARACTERISTICS

Production Data Rev 1.0

Test Conditions:

R

L

= 10kΩ, C

L

= 100pF. AVDD = DVDD = 5V

±

10%, V

REF

= 2.048V and AVDD = DVDD = 3V

±

10%, V

REF

= 1.024V over

recommended operating free-air temperature range (unless noted otherwise)

PARAMETER

Static DAC Specifications

Resolution

Integral non-linearity

Differential non-linearity

Zero code error

Gain error

D.c power supply rejection ratio

Zero code error temperature

coefficient

Gain error temperature coefficient

DAC Output Specifications

Output voltage range

Output load regulation

Power Supplies

Active supply current

IDD

No load, VIH = DVDD, VIL = 0V

AVDD = DVDD = 5V,

V

REF

= 2.048V See Note 8

Slow

Fast

AVDD = DVDD = 3V,

V

REF

= 1.024V

Slow

Fast

Power down supply current

Dynamic DAC Specifications

Slew rate

DAC code 128 to 4095,

10%-90% See Note 10

Slow

Fast

Settling time

DAC code 128 to 4095

Slow

Fast

Glitch energy

Signal to noise ratio

SNR

Code 2047 to code 2048

f

S

= 480ksps,

f

OUT

= 1kHz BW = 20kHz,

TA = 25°C See Note 12

f

S

= 480ksps,

f

OUT

= 1kHz BW = 20kHz,

TA = 25°C See Note 12

f

S

= 480ksps,

f

OUT

= 1kHz BW = 20kHz,

TA = 25°C See Note 12

f

S

= 480ksps,

f

OUT

= 1kHz BW = 20kHz, T

A

=

25°C See Note 12

60

65

1.5

8

3.5

1.0

1

78

V/µs

µs

nV-s

dB

No load, all digital inputs 0V

or DVDD. See Note 9

0.4

1.4

0.01

1.1

2.7

10

mA

µA

0.5

1.6

1.3

3.0

mA

2kΩ to 10kΩ load. See Note 7

0

0.1

AVDD - 0.4

0.3

V

%

INL

DNL

ZCE

GE

d.c. PSRR

See Note 1

See Note 2

See Note 3

See Note 4

See Note 5

See Note 6

12

bits

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

±

1.5

±

0.4

3

±

4

±

1

±

20

±

0.5

LSB

mV

% FSR

mV/V

ppm/°C

±

0.25

0.5

3

1

Signal to noise and distortion ratio

SNRD

58

69

dB

Total harmonic distortion

THD

-68

-60

dB

Spurious free dynamic range

SPFDR

72

dB

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June 1999

4

Production Data

WM2613

Test Conditions:

R

L

= 10kΩ, C

L

= 100pF. AVDD = DVDD = 5V

±

10%, V

REF

= 2.048V and AVDD = DVDD = 3V

±

10%, V

REF

= 1.024V over

recommended operating free-air temperature range (unless noted otherwise)

PARAMETER

Reference

Reference input resistance

Reference input capacitance

Reference feedthrough

Reference input bandwidth

RREFIN

CREFIN

VREF = 1V

PP

at 1kHz

+ 1.024V d.c., DAC code 0

VREF = 0.2V

PP

+ 1.024V d.c.

DAC code 2048

Slow

Fast

Digital Inputs

High level input current

Low level input current

Input capacitance

Notes:

1.

2.

Integral non-linearity (INL)

is the maximum deviation of the output from the line between zero and full scale excluding the

effects of zero code and full scale errors).

Differential non-linearity (DNL)

is the difference between the measured and ideal 1LSB amplitude change

of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same

direction (or remains constant) as a change in digital input code.

Zero code error

is the voltage output when the DAC input code is zero.

Gain error

is the deviation from the ideal full scale output excluding the effects of zero code error.

Power supply rejection ratio

is measured by varying AVDD from 4.5V to 5.5V and measuring the

proportion of this signal imposed on the zero code error and the gain error.

Zero code error

and

Gain error

temperature coefficients are normalised to full scale voltage.

Output load regulation

is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ

load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

I

DD

is measured while continuously writing code 2048 to the DAC. For V

IH

< DVDD - 0.7V and V

IL

> 0.7V supply current

will increase.

Typical supply current

in power down mode is 10nA. Production test limits are wider for speed of test.

Slew rate

results are for the lower value of the rising and falling edge slew rates.

Settling time

is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and

falling edges. Limits are ensured by design and characterisation, but are not production tested

SNR, SNRD, THD

and

SPFDR

are measured on a synthesised sinewave at frequency f

OUT

generated with

a sampling frequency f

S

.

I

IH

I

IL

C

I

Input voltage = DVDD

Input voltage = 0V

8

1

-1

µA

pF

1

1.6

MHz

10

5

-60

MΩ

pF

dB

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June 1999

5

WM2613

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