Features
•
Monolithic Field Programmable System Level Integrated Circuit
•
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR
®
Core and
Extensive Data and Instruction SRAM
10,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
™
– 4.6K - 18.4K Bits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic
®
Designs
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
Patented AVR Enhanced RISC Architecture
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Over 30 MIPS Performance Available
– “C” Code Optimized Architecture with 32 x 8 General Purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
36K Bytes of Dynamically Allocated Instruction and Data SRAM
– Up to 16K x 16 Internal 15 ns Instructions SRAM
– Up to 16K x 8 Internal 15 ns Data SRAM
AVR Fixed Peripherals
– Industry-standard two-wire Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9-, or 10-bit PWM
Support for FPGA Custom Peripherals
– AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible
to FPGA
– FPGA Macro Library of Custom Peripherals
16 FPGA Supplied Internal Interrupts to AVR
Up to 4 External Interrupts to AVR
8 Global FPGA Clocks
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
Multiple Oscillator Circuits
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
V
CC
: 3.0V - 3.6V
3.3V 33 MHz PCI Compliant FPGA I/O
– 24 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
Pin-compatible with the Atmel AT40K Series FPGAs
High-performance, Low-power 0.35µ CMOS five Layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
•
•
•
10K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller
and 36K Bytes
of SRAM
AT94K Series
Field
Programmable
System Level
Integrated
Circuit
Advance
Information
•
•
•
•
•
•
•
•
•
•
Description
The AT94K Series (FPSLIC family) shown in Table 1 is a combination of the popular
Atmel AT40K series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC
microcontroller with standard peripherals. Extensive data and instruction SRAM as
well as device control and management logic are included on this monolithic device,
fabricated on Atmel’s 0.35µ five-layer metal CMOS process.
(continued)
Rev. 1138CS–12/99
Note: This is a summary document. For the complete 130-page
document, please visit our web site at
www.atmel.com
or e-mail at
1
literature@atmel.com
and request literature #1138B.
The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchro-
nous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable
without loss of data) and 10,000 to 40,000 usable gates.
Table 1.
The AT94K Series
Device
FPGA Gates
FPGA Core Cells
FPGA SRAM Bits
FPGA Registers (Total)
Max FPGA User I/O
AVR Programmable I/O Lines
Programmable SRAM Bytes
Data SRAM Bytes
Hardware Multiplier (8-bit)
Two-wire Serial Interface
UART
Watchdog Timer
Timer/Counters
Real-time Clock
Typical AVR throughput @ 40 MHz
Operating Voltage
AT94K10
10K
576
4096
864
144
16
20K - 32K
4K - 16K
Yes
Yes
2
Yes
3
Yes
30 MIPS
3.0 - 3.6V
AT94K20
20K
1024
8192
1408
192
16
20K - 32K
4K - 16K
Yes
Yes
2
Yes
3
Yes
30 MIPS
3.0 - 3.6V
AT94K40
40K
2304
18432
2880
288
16
20K - 32K
4K - 16K
Yes
Yes
2
Yes
3
Yes
30 MIPS
3.0 - 3.6V
Figure 1.
AT94K Architecture
PROGRAMMABLE I/O
10 - 40K Gates FPGA
16K X 16
Program
SRAM Memory*
16 Interrupt Lines
4 Interrupt Lines
2-wire Serial
Unit
I/O
I/O
with
Multiply.
Two 8-bit
Timer/Counters
4096 x 8
Data
SRAM*
16 Prog. I/O
Lines
I/O
16 Addr
Decoder
*Part of program and data
memory can be interchanged.
2
AT94K Family
AT94K Family
The embedded AVR core, by executing powerful instruc-
tions in a single-clock-cycle, achieves throughputs
approaching 1 MIPS per MHz allowing System Designers
to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture
that combines a rich instruction set with 32 general-pur-
pose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruc-
tion executed in one clock-cycle. The resulting architecture
is more code-efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers at the
same CLK frequency. The AVR executes out of on-chip
SRAM. Both the FPGA configuration SRAM and AVR
instruction code SRAM can be automatically loaded at sys-
tem power-up using Atmel’s in-system programmable
AT17 series EEPROM configuration memories.
State-of-the-art FPSLIC design tools “System Designer”
were developed in conjunction with the FPSLIC architec-
ture to help reduce overall time-to-market by integrating
microcontroller development and debug, FPGA develop-
ment and place and route and complete system
co-verification in one easy-to-use software tool.
3
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© Atmel Corporation 1999.
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