KM44S32030AN-FL datasheet, PDF

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KM44S32030AN-FL: DescriptionSynchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54; Categorystorage storage; File Size102KB，10 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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KM44S32030AN-FL Overview

Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54

KM44S32030AN-FL Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
JESD-30 code	R-PDSO-G54
length	11.2 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	DUAL
width	10.16 mm

KM44S32030AN-FL Preview

shrink-TSOP

KM44S32030AN

Preliminary

CMOS SDRAM

128Mb SDRAM

Shrink TSOP

8M x 4Bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.1

April 1999

Samsung Electronics reserves the right to change products or specification without notice.

REV. 0.1 Apr. 1999

shrink-TSOP

KM44S32030AN

Revision History

Version 0.0 (April 21. 1999,

Preliminary)

• Preliminary specification for shrink-TSOP(STSOP).

• Based on the standard TSOP-II specification(KM44S32030AT, Rev. 0.0, April 19. 1999).

Preliminary

CMOS SDRAM

Version 0.1 (April 22. 1999,

Preliminary)

• Changed package length from 11.00mm to 11.20mm in the page of

PACKAGE DIMENSIONS.

REV. 0.1 Apr. 1999

shrink-TSOP

KM44S32030AN

Preliminary

CMOS SDRAM

8M x 4Bit x 4 Banks Synchronous DRAM in New Shrink-TSOP(sTSOP)

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

- CAS latency (2 & 3)

- Burst length (1, 2, 4, 8 & Full page )

- Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K Cycle)

GENERAL DESCRIPTION

The

KM44S32030

AN is 134,217,728 bits synchronous high

data rate Dynamic RAM organized as 4 x 8,388,608 words by 4

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programma-

ble burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

54pin

sTSOP

KM44S32030AN-G/FA 133MHz(CL=3)

KM44S32030AN-G/F8 125MHz(CL=3)

KM44S32030AN-G/FH 100MHz(CL=2)

KM44S32030AN-G/FL 100MHz(CL=3)

LVTTL

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

8M x 4

Sense AMP

8M x 4

Refresh Counter

Output Buffer

Row Decoder

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

Latency & Burst Length

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

Samsung Electronics reserves the right to change products or specification without notice.

REV. 0.1 Apr. 1999

shrink-TSOP

KM44S32030AN

PIN CONFIGURATION

(Top view)

N.C

DDQ

N.C

DQ0

SSQ

N.C

DDQ

N.C

DQ1

SSQ

N.C

CAS

RAS

BA0

BA1

A10/AP

Preliminary

CMOS SDRAM

54Pin sTSOP

(400mil x 441mil)

(0.4 mm Pin pitch)

N.C

SSQ

N.C

DQ3

DDQ

N.C

SSQ

N.C

DQ2

DDQ

N.C

N.C/RFU

DQM

CLK

CKE

N.C

A11

PIN FUNCTION DESCRIPTION

CLK

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

, CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No Connection on the device.

CKE

Clock enable

~ A

~ BA

RAS

CAS

DQM

DDQ

SSQ

N.C/RFU

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

No connection

/reserved for future use

REV. 0.1 Apr. 1999

shrink-TSOP

KM44S32030AN

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

, V

DDQ

STG

Value

-1.0 ~ 4.6

-55 ~ +150

Preliminary

CMOS SDRAM

Unit

°C

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

= -2mA

= 2mA

Note

Notes :

1. V

(max) = 5.6V AC.The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

RAS, CAS, WE, CS, CKE, DQM

Address

~ DQ

Notes :

1. -A only specify a maximum value of 3.5pF

2. -A only specify a maximum value of 3.8pF

3. -A only specify a maximum value of 6.0pF

REV. 0.1 Apr. 1999

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

KM44S32030AN-FL Related Products

	KM44S32030AN-FL	KM44S32030AN-FA	KM44S32030AN-G	KM44S32030AN-F8	KM44S32030AN-FH
Description	Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54	Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP,	TSOP,	TSOP,	TSOP,	TSOP,
Contacts	54	54	54	54	54
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	5.4 ns	5.4 ns	6 ns	6 ns
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
length	11.2 mm	11.2 mm	11.2 mm	11.2 mm	11.2 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	4	4	4	4	4
Number of functions	1	1	1	1	1
Number of ports	1	1	1	1	1
Number of terminals	54	54	54	54	54
word count	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32MX4	32MX4	32MX4	32MX4	32MX4
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP	TSOP	TSOP	TSOP	TSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.4 mm	0.4 mm	0.4 mm	0.4 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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