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AN-6747
Applying FAN6747 to Control a Flyback Power Supply with
Peak Current Output
1. Introduction
Highly integrated PWM controller, FAN6747, is optimized
for applications with motor load, such as printers and
scanners, that inherently impose some kind of overload
condition on the power supply during acceleration mode.
FAN6747 provides a two-level OCP function that allows the
SMPS to stably deliver peak power during the motor
acceleration without causing premature shutdown, while
protecting the SMPS from overload condition.
Green-mode and burst-mode functions with a low operating
current maximize the light-load efficiency so that the power
supply can meet stringent standby power regulations.
The frequency-hopping function reduces electro-magnetic
interference (EMI) of a power supply by spreading the
energy over a wider frequency range. The constant power
limit function minimizes the component stress in abnormal
condition and helps optimize the power stage. Protection
functions such as OCP, OLP, OVP, and OTP are fully
integrated into FAN6747, which improves the SMPS
reliability without increasing system cost.
This application note presents design considerations to
apply FAN6747 to a flyback power supply with peak load
current profile. It covers designing the transformer, selecting
the components, and closing the feedback loop. Figure 1
shows a typical application circuit using FAN6747.
Figure 1.
Typical Application
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 9/16/10
www.fairchildsemi.com
AN-6747
APPLICATION NOTE
2. Design Considerations
Flyback converters have two operation modes; continuous
conduction mode (CCM) and discontinuous conduction
mode (DCM). CCM and DCM each have advantages and
disadvantages. In general, DCM provides better switching
conditions for the rectifier diodes, since the diodes are
operating at zero current just before becoming reverse
biased and the reverse recovery loss is minimized. The
transformer size can be reduced using DCM because the
average energy storage is low compared to CCM. However,
DCM causes high RMS current, which increases the
conduction loss of the MOSFET severely for low line
condition. Thus, especially for applications with peak load
profile, such as printer and scanner; it is typical to design
the converter such that the converter operates in CCM for
low line and peak load condition to maximize efficiency.
In this section, a design procedure is presented using the
schematic of Figure 1 as a reference. An offline SMPS with
20W/32V nominal output power and 70W/32V peak output
power has been selected as a design example.
[STEP-1] Define the System Specifications
Designing a power supply with peak load current profile,
the following specifications should be determined first:
Line voltage range (V
LINEMIN
and
V
LINEMAX
)
Line frequency (f
L
)
Nominal output power (P
NO
)
Peak output power (P
PO
) and its duration (t
PO
)
Estimated efficiencies for nominal load (η
N
) and peak
load (η
P
).
The power conversion efficiency must be estimated to
calculate the input powers for each condition. Typically,
the efficiency at peak load condition is lower than that
of nominal load since most of the components of power
supply are selected for nominal load condition.
If no reference data is available, set
η
N
= 0.7~0.75 and
η
P
= 0.65~0.7 for low-voltage output applications and
η
N
= 0.8~0.85 and
η
P
= 0.75~0.8 for high-voltage
output applications.
With the estimated efficiency, the input power for peak
load condition is given by:
P
INP
=
P
PO
η
P
(Design Example)
The specifications of the target
system are:
V
LINEMIN
=90V
RMS
,
V
LINEMAX
=264V
RMS
Line frequency (f
L
) = 60Hz
Nominal output power (P
NO
) = 20W (32V/0.625A)
Peak output power (P
PO
) = 70W (32V/2.187A)
Peak load duration (t
PO
) < 100ms
Estimated efficiency:
η
N
= 0.87 and
η
P
= 0.83
P
INP
=
P
PO
70
=
=
84 W
η
P
0.83
P
NO
20
=
=
23 W
η
N
0.87
P
INN
=
FAN6747 can be used for this application because the
peak load duration is less than the OCP delay time of
220ms.
[STEP-2] Determine the Input Capacitor (C
IN
) and
the Input Voltage Range
It is typical to select the input capacitor as 1.5~2μF per watt
of peak input power for universal input range (85-265V
RMS
)
and 0.7~0.8μF per watt of peak input power for European
input range (195V-265V
RMS
). With the input capacitor
chosen, the minimum input capacitor voltage at peak load
condition is obtained as:
V
INPMIN
=
2
•
V
LINE MIN
(
)
2
−
P
INP
•
(
1
−
D
CH
)
C
IN
•
f
L
(
3
)
The minimum input capacitor voltage at nominal load
condition is obtained as:
V
INNMIN
=
2
•
V
LINE MIN
(
)
2
−
P
INN
•
(
1
−
D
CH
)
C
IN
•
f
L
(
4
)
where
D
CH
is the input capacitor charging duty ratio defined
as shown in Figure 2, which is typically about 0.2.
The maximum input capacitor voltage is given as:
V
INMAX
=
2 V
LINEMAX
(
5
)
(
1
)
The input power for nominal load condition is given
by:
P
INN
=
P
NO
η
N
(
2
)
Figure 2.
Input Capacitor Voltage Waveform
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 9/16/10
www.fairchildsemi.com
2
AN-6747
APPLICATION NOTE
(Design Example)
By choosing a 120μF capacitor for
the input capacitor, the minimum input voltages for peak
and nominal load are obtained, respectively, as:
V
INPMIN
=
2
•
V
LINE MIN
=
2
•
(
90
)
2
−
(
)
2
−
P
INP
•
(
1
−
D
CH
)
C
IN
•
f
L
=
83 V
84
•
(
1
−
0.2
)
120
×
10
−
6
•
60
V
INNMIN
=
2
•
V
LINE MIN
=
2
•
(
90
)
2
−
(
)
2
−
P
INN
•
(
1
−
D
CH
)
C
IN
•
f
L
=
117 V
As can be seen in Equation (7), the voltage stress across the
MOSFET can be reduced by reducing V
RO
; however, this
increases the voltage stresses on the rectifier diodes in the
secondary side. Therefore,
V
RO
should be determined by a
trade-off between the voltage stresses of MOSFET and
diode. Because the actual drain voltage rises above the
nominal MOSFET voltage due to the leakage inductance of
the transformer, as shown in Figure 3, it is typical to set
V
RO
around 70~100V so that
V
DSNOM
is 430~450V for 600V
MOSFET (73~78% of MOSFET voltage rating).
(Design Example)
By determining V
RO
as 100V:
23
•
(
1
−
0.2
)
120
×
10
−
6
•
60
D
MAX
=
V
RO
V
RO
+
V
INP MIN
=
100
=
0.55
100
+
83
The maximum input voltage is obtained as:
V
INMAX
=
2
•
V
LINEMAX
=
2
•
264
=
373V
V
DSNOM
=
V
INMAX
+
V
RO
=
373
+
100
=
473V
[STEP-3] Determine the Reflected Output Voltage
(V
RO
)
When the MOSFET is turned off, the input voltage (V
IN
),
together with the output voltage reflected to the primary,
(V
RO
) are imposed across the MOSFET, as shown in Figure
3. With a given V
RO
, the maximum duty cycle (D
MAX
) and
the maximum nominal MOSFET voltage (V
DSNOM
) are
obtained as:
D
MAX
=
V
RO
V
RO
+
V
INP MIN
[STEP-4] Determine the Transformer Primary-Side
Inductance (L
M
)
The transformer primary-side inductance is determined for
the minimum input voltage and peak load condition. With
the D
MAX
from step 3, the primary-side inductance (L
M
) of
the transformer is obtained as:
L
M
(
V
=
INP
•
D
MAX
2P
INP
f
SW
K
RF
MIN
)
2
(
8
)
(
6
)
(
7
)
where
f
SW
is the switching frequency and
K
RF
is the ripple
factor at peak load and minimum input voltage condition, as
shown in Figure 4.
The ripple factor is closely related to the transformer size
and the RMS value of the MOSFET current. Even though
the conduction loss in the MOSFET can be reduced by
reducing the ripple factor, too small a ripple factor forces an
increase in transformer size. From a practical point of view,
it is reasonable to set
K
RF
= 0.3~0.6 for the universal input
range and
K
RF
= 0.4~0.8 for the European input range.
Once
L
M
is calculated by determining K
RF
from Equation
(8), the peak current and RMS current of the MOSFET for
minimum input voltage and peak load condition are
obtained as:
I
DS PK
=
I
EDC
+
Δ
I
2
V
DS
NOM
=
V
INMAX
+
V
RO
(
9
)
(
10
)
(
11
)
(
12
)
I
DS
RMS
=
2
⎡
⎛ Δ
I
⎞ ⎤
D
MAX
2
⎢
3
(
I
EDC
)
+ ⎜ ⎟ ⎥
⎝
2
⎠ ⎥
3
⎢
⎣
⎦
where
and
I
EDC
=
V
INP
P
INP
MIN
•
D
MAX
V
INP MIN
D
MAX
Δ
I
=
L
M
f
SW
Figure 3.
Output Voltage Reflected to the Primary
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© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 9/16/10
AN-6747
APPLICATION NOTE
K
RF
Δ
I
Δ
I
=
2
I
EDC
The peak drain current at minimum input voltage and peak
load condition was obtained from Equation (9) in step 4.
The peak drain current at minimum input voltage and
nominal load condition is given as:
CCM:
I
D
S
PK
Figure 4.
MOSFET Current and Ripple Factor (K
RF
)
I
DS.N
PK
=
P
INN
•
V
INMIN
+
V
RO
V
INNMIN
•
V
RO
(
)
+
V
INNMIN
•
V
RO
2L
M
f
SW
•
V
INNMIN
+
V
RO
(
)
(
13
)
DCM:
I
DS.NPK
=
2
•
P
INN
f
SW
•
L
M
(Design Example)
Determining the ripple factor as 0.375:
(
14
)
L
M
(
V
=
INP
•
D
MAX
2P
INP
f
SW
K
RF
MIN
)
2
=
(
83
•
0.55
)
2
2
•
84
•
65
×
10
•
0.375
3
=
508
μ
H
Whether the converter operates in CCM or DCM at
minimum input voltage and nominal load condition is
determined by:
CCM:
2P
INN
L
M
f
SW
•
I
EDC
=
Δ
I
=
P
INP
V
INP
MIN
•
D
MAX
=
84
=
1.84A
83
•
0.55
(
V
MIN
MIN
MIN
MIN
INN
+
V
RO
•
V
RO
+
V
RO
•
V
RO
)
>
1
(
15
)
V
INN
V
INP
D
MAX
83
•
0.55
=
=
1.38 A
L
M
f
SW
508
×
10
−
6
•
65
×
10
3
Δ
I
=
1.84
+
0.69
=
2.53
2
MIN
DCM:
2P
INN
L
M
f
SW
•
(
V
INN
)
<
1
(
16
)
I
DS PK
=
I
EDC
+
V
INN
The condition for the sensing resistor is given as:
R
CS
<
R
CS
<
0.48
I
DS.NPK
0.825
I
DS.NPK
I
DS
RMS
2
⎤
⎡
D
2
⎛ Δ
I
⎞
= ⎢
3
(
I
EDC
)
+ ⎜ ⎟ ⎥
MAX
⎢
⎝
2
⎠ ⎥
3
⎣
⎦
2
(
17
)
(
18
)
=
[
3
(
1.84
)
+
(
0.69
)
2
]
0.55
=
1 .4 A
3
(Design Example)
For minimum input voltage and
[STEP-5] Determine the Sensing Resistor Value
The current sensing resistor value should be determined
considering the over-current protection threshold and the
pulse-by-pulse current limit threshold, as shown in Figure
5. The peak value of current sensing voltage (V
CS
) should
be lower than the pulse-by-pulse current limit level for peak
load condition. It should be lower than the OCP threshold
for nominal load conditions to prevent false triggering of
OCP protection during normal operation.
Pulse-by-Pulse Current Limit Threshold
0.825V
Peak Power
Condition
nominal load condition, the operation mode is DCM as:
2P
INN
L
M
f
SW
=
(
V
•
MIN
MIN
INN
+
V
RO
•
V
RO
)
V
INN
2
•
23
•
508
×
10
−
6
•
65
×
10
3
•
(
117
+
100
117
•
100
)
<
1
The peak drain current at minimum input voltage and
nominal power condition is given as:
I
DS.NPK
=
2
•
P
INN
=
f
SW
•
L
M
2
•
23
65
×
10
3
•
508
×
10
−
6
=
1.18 A
The conditions for the sensing resistor are given as:
0.48V
OCP Threshold
Nominal Power
Condition
R
CS
<
R
CS
<
0.48
I
DS.NPK
0.825
I
DS.P PK
=
0.48
=
0.41
Ω
1.18
0.825
=
0.33
Ω
2.53
=
V
CS
=
I
DS
⋅
R
CS
Figure 5.
Determining Current Sensing Resistor
A 0.33Ω resistor is selected for the current-sensing resistor.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 9/16/10
www.fairchildsemi.com
4
AN-6747
APPLICATION NOTE
[STEP-6] Determine the Minimum Primary Turns
With a given core, the minimum number of turns for the
transformer primary side to avoid the core saturation is
given by:
N
P MIN
=
L
•
0 . 825 / R
CS
L
M
I
LIM
×
10
6
=
M
×
10
6
B
SAT
A
e
B
SAT
A
e
2
n
=
V
RO
N
P
=
N
S
V
O
+
V
F
(
20
)
(
19
)
where
N
P
and
N
S
are the number of turns for primary side
and secondary side, respectively,
V
O
is the output voltage;
and
V
F
is the diode (D
O
) forward-voltage drop.
Determine the proper integer for
N
S
such that the resulting
N
P
is larger than
N
Pmin
obtained from Equation (19).
The number of turns for the auxiliary winding for V
DD
supply is determined as:
N
A
=
V
DD
*
+
V
FA
•
N
S
V
O
+
V
F
(21)
where
A
e
is the cross-sectional area of the core in mm , I
LIM
is the pulse-by-pulse current limit level determined by
0.825V threshold, R
CS
is current sensing resistor, and
B
SAT
is the saturation flux density in Tesla.
The pulse-by-pulse current limit level is included in
Equation (19) because the inductor current reaches the
pulse-by-pulse current limit level during the load transient
or overload condition. Figure 6 shows the typical
characteristics of ferrite core from TDK (PC40). Since the
saturation flux density (B
SAT
) decreases as the temperature
rises, the high-temperature characteristics should be
considered. If there is no reference data, use
B
MAX
=0.3T.
where
V
DD
is the nominal value of the supply voltage and
V
FA
is the forward-voltage drop of
D
DD
as defined in Figure
7. Since V
DD
increases as the output load increases, it is
proper to set
V
DD
at 3~5V higher than V
DD
UVLO level (9V)
to avoid the over-voltage protection condition during the
peak load operation.
Figure 7.
Figure 6. Typical B-H Characteristics of Ferrite Core
(TDK/PC40)
Simplified Transformer Diagram
(Design Example)
Assuming the diode forward-
with effective cross-sectional area of 78mm
2
. Choosing
the saturation flux density as 0.27T, the minimum
number of turns for the primary side is obtained as:
N
P MIN
=
L
M
•
0.825 / R
CS
508
×
10
•
0 .825 / 0.33
×
10
6
=
×
10
6
=
60
B
SAT
A
e
0.27
•
78
−
6
(Design Example)
An EF25/13/11 core is selected
voltage drop is 1V, the turn ratio is obtained as:
n
=
V
RO
N
P
100
=
=
=
3.03
N
S
V
O
+
V
F
32
+
1
Then, determine the proper integer for
N
S
such that the
resulting
N
P
is larger than
N
Pmin
as:
N
S
=
20,N
P
=
n
•
N
S
=
61
>
N
PMIN
[STEP-7] Determine the Number of Turns for Each
Winding
Figure 7 shows a simplified diagram of the transformer.
First, calculate the turn ratio (n) between the primary side
and the secondary side from the reflected output voltage
determined in step 3 as:
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 9/16/10
5
Setting V
DD
* as 13V, the number of turns for the
auxiliary winding is obtained as:
N
A
=
V
DD
*
+
V
FA
13
+
1
•
20
=
9
•
N
S
=
32
+
1
V
O
+
V
F
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