FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
November 2010
FAN5236
Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Features
Highly Flexible, Dual Synchronous Switching PWM
Controller that Includes Modes for:
Description
The FAN5236 PWM controller provides high efficiency
and regulation for two output voltages adjustable in the
range of 0.9V to 5.5V required to power I/O, chip-sets,
and memory banks in high-performance notebook
computers,
PDAs,
and
Internet
appliances.
Synchronous rectification and hysteretic operation at
light loads contribute to high efficiency over a wide
range of loads. The Hysteretic Mode can be disabled
separately on each PWM converter if PWM Mode is
desired for all load levels. Efficiency is enhanced by
using MOSFET R
DS(ON)
as a current-sense component
.
Feedforward ramp modulation, average-current-mode
control scheme, and internal feedback compensation
provide fast response to load transients. Out-of-phase
operation with 180-degree phase shift reduces input
current ripple. The controller can be transformed into a
complete DDR memory power supply solution by
activating a designated pin. In DDR mode, one of the
channels tracks the output voltage of another channel
and provides output current sink and source capability
— essential for proper powering of DDR chips. The
buffered reference voltage required by this type of
memory is also provided. The FAN5236 monitors these
outputs and generates separate PGx (power good)
signals when the soft-start is completed and the output
is within ±10% of the set point. Built-in over-voltage
protection prevents the output voltage from going above
120% of the set point. Normal operation is automatically
restored when the over-voltage conditions cease.
Under-voltage protection latches the chip off when
output drops below 75% of the set value after the soft-
start sequence for this output is completed. An
adjustable over-current function monitors the output
current by sensing the voltage drop across the lower
MOSFET. If precision current-sensing is required, an
external current-sense resistor may be used.
-
-
-
DDR Mode with In-phase Operation for
Reduced Channel Interference
90° Phase-shifted, Two-stage DDR Mode for
Reduced Input Ripple
Dual Independent Regulators, 180° Phase
Shifted
V
TT
Tracks V
DDQ/2
V
DDQ/2
Buffered Reference Output
Complete DDR Memory Power Solution
-
-
Lossless Current Sensing on Low-side MOSFET or
Precision Over-Current Using Sense Resistor
V
CC
Under-Voltage Lockout
Converters can Operate from +5V or 3.3V or
Battery Power Input (5V to 24V)
Excellent Dynamic Response with Voltage
Feedforward and Average-Current-Mode Control
Power-Good Signal
Supports DDR-II and HSTL
Light-Load Hysteretic Mode Maximizes Efficiency
TSSOP28 Package
Applications
DDR V
DDQ
and V
TT
Voltage Generation
Mobile PC Dual Regulator
Server DDR Power
Hand-held PC Power
Related Resources
Application Note — AN-6002 Component
Calculations and Simulation Tools for FAN5234 or
FAN5236
Application Note — AN-1029 Maximum Power
Enhancement Techniques for SO-8 Power
MOSFET
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Ordering Information
Part Number
FAN5236MTCX
Operating
Temperature
Range
-10 to +85°C
Package
28-Lead Thin-Shrink Small-Outline Package (TSSOP)
Packing Method
Tape and Reel
Block Diagrams
+5
VCC
FAN5236
V
IN
(BATTERY)
= 5 to 24V
Q1
ILIM1
L
OUT1
V
O UT1
= 2.5V
C
OUT1
PWM 1
Q2
DDR
Q3
ILIM2/
REF2
L
OUT2
V
O UT 2
= 1.8V
C
OUT2
PWM 2
Q4
Figure 1. Dual-Output Regulator
+5
VCC
FAN5236
V
IN
(BATTERY)
= 5 to 24V
Q1
ILIM1
L
OUT1
V
DDQ
= 2.5V
C
OUT1
R
PWM 1
Q2
+5
DDR
Q3
R
V
TT
=
V
DDQ /2
C
OUT2
PG2/REF
1.25V
L
OUT2
PWM 2
Q4
IL IM2/REF2
Figure 2. Complete DDR Memory Power Supply
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
2
FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Pin Configuration
AGND
LDRV1
PGND1
SW1
HDRV1
BOOT1
ISNS1
EN1
FPWM1
VSEN1
ILIM1
SS1
DDR
VIN
1
2
3
4
5
6
28
27
26
25
24
23
VCC
LDRV2
PGND2
SW2
HDRV2
BOOT2
ISNS2
EN2
FPWM2
VSEN2
ILIM2/REF2
SS2
PG2/REF2OUT
PG1
7
22
FAN5236
8
21
9
10
11
12
13
14
20
19
18
17
16
15
Figure 3. Pin Configuration
Pin Definitions
Pin #
1
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12
17
Name
AGND
LDRV1
LDRV2
PGND1
PGND2
SW1
SW2
HDRV1
HDRV2
BOOT1
BOOT2
ISNS1
ISNS2
EN1
EN2
FPWM1
FPWM2
VSEN1
VSEN2
ILIM1
SS1
SS2
Description
Analog Ground.
This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
Low-Side Drive.
The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
Power Ground.
The return for the low-side MOSFET driver. Connect to source of low-side
MOSFET.
Switching Node.
Return for the high-side MOSFET driver and a current sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
High-Side Drive.
High-side (upper) MOSFET driver output. Connect to gate of high-side
MOSFET.
BOOT.
Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.
Current-Sense Input.
Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
Enable.
Enables operation when pulled to logic HIGH. Toggling EN resets the regulator
after a latched fault condition. These are CMOS inputs whose state is indeterminate if left
open.
Forced PWM Mode.
When logic LOW, inhibits the regulator from entering Hysteretic Mode;
otherwise tie to V
OUT
. The regulator uses V
OUT
on this pin to ensure a smooth transition from
Hysteretic Mode to PWM Mode. When V
OUT
is expected to exceed V
CC
, tie to V
CC
.
Output Voltage Sense.
The feedback from the outputs. Used for regulation as well as PG,
under-voltage, and over-voltage protection and monitoring.
Current Limit 1.
A resistor from this pin to GND sets the current limit.
Soft Start.
A capacitor from this pin to GND programs the slew rate of the converter during
initialization. During initialization, this pin is charged with a 5mA current source.
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
3
FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Pin Descriptions
(Continued)
Pin #
13
Name
DDR
Description
DDR Mode Control.
HIGH = DDR Mode. LOW = two separate regulators operating 180° out
of phase.
Input Voltage.
Normally connected to battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
Power Good Flag.
An open-drain output that pulls LOW when V
SEN
is outside a ±10%
range of the 0.9V reference.
Power Good 2.
When not in DDR Mode, open-drain output that pulls LOW when the V
OUT
is
out of regulation or in a fault condition.
Reference Out 2.
When in DDR Mode, provides a buffered output of REF2. Typically used
as the V
DDQ/2
reference.
14
VIN
15
PG1
16
PG2 /
REF2OUT
18
Current Limit 2.
When not in DDR Mode, a resistor from this pin to GND sets the current
ILIM2 / REF2 limit.
Reference
for reg #2 when in DDR Mode. Typically set to V
OUT1 / 2
.
VCC
VCC.
This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
28
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
4
FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
Parameter
V
CC
Supply Voltage
V
IN
Supply Voltage
BOOT, SW, ISNS, HDRV
BOOTx to SWx
All Other Pins
Min.
Max.
6.5
27
33
6.5
Unit
V
V
V
V
V
ºC
ºC
ºC
-0.3
-40
-65
V
CC
+0.3
+150
+150
+300
T
J
T
STG
T
L
Junction Temperature
Storage Temperature
Lead Temperature (Soldering,10 Seconds)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
T
A
Θ
JA
Parameter
V
CC
Supply Voltage
V
IN
Supply Voltage
Ambient Temperature
Thermal Resistance, Junction to Ambient
Min.
4.75
-10
Typ.
5.00
Max.
5.25
24
+85
90
Unit
V
V
°C
°C/W
© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
www.fairchildsemi.com
5
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