www.fairchildsemi.com
AN-6861
Applying FAN6861 to a Flyback Power Supply with Peak
Load Current Profile
1. Introduction
Highly integrated PWM controller, FAN6861, is optimized
for applications with motor load, such as printers and
scanners, that inherently impose some kind of overload
condition on the power supply during acceleration mode.
The two-level OCP function allows the SMPS to stably
deliver peak power during the motor acceleration without
causing premature shutdown, while protecting the SMPS
from overload condition.
The green-mode and burst-mode functions with a low
operating current (2.2mA maximum in green mode)
maximize the light-load efficiency so that the power supply
can meet stringent standby power regulations.
The frequency-hopping function reduces electro-magnetic
interference (EMI) of a power supply by spreading the
energy over a wider frequency range. The constant power
limit function minimizes the component stress in abnormal
condition and helps to optimize the power stage. Protection
functions; such as OCP, OLP, OVP, and OTP are fully
integrated into FAN6861, which improves the SMPS
reliability without increasing system cost.
This application note presents design considerations to apply
FAN6861 to a flyback power supply with peak load current
profile. It covers designing the transformer, selecting the
components, and closing the feedback loop. Figure 1 shows
a typical application circuit using FAN6861.
L
EMI
AC input
R
SN1
+
R
SN2
C
SN2
C
SN1
D
OUT
V
IN
D
DD1
R
START
5
+
+
Filter
V
O +
V
O -
N
C
IN
C
OUT 1
R
DAMP
+
D
DD 2
D
SN
C
OUT 2
C
DD 1
C
DD 2
R
G
VDD
3
RT
GATE
6
SENSE
4
GND
1
2
FB
R
CSF
C
CSF
C
FB
R
CS
FAN6861
R
BIAS
R
1
R
DB
C
F
R
2
KA431
Figure 1. Typical Application
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 6/9/09
www.fairchildsemi.com
AN-6861
APPLICATION NOTE
2. Design Considerations
Flyback converters have two operation modes; continuous
conduction mode (CCM) and discontinuous conduction
mode (DCM). CCM and DCM have their own advantages
and disadvantages, respectively. In general, DCM provides
better switching conditions for the rectifier diodes, since the
diodes are operating at zero current just before becoming
reverse biased and the reverse recovery loss is minimized.
The transformer size can be reduced using DCM because
the average energy storage is low compared to CCM.
However, DCM inherently causes high RMS current, which
increases the conduction loss of the MOSFET severely for
low line condition. Thus, especially for applications with
peak load profile, such as printer and scanner; it is typical to
design the converter such that the converter operates in
CCM for low line and peak load condition to maximize
efficiency.
In this section, a design procedure is presented using the
schematic of Figure 1 as a reference. An off line SMPS with
20W/32V nominal output power and 50W/32V peak output
power has been selected as a design example.
(Design Example)
The specifications of the target
system are:
•
V
LINEMIN
=90V
RMS
V
LINEMAX
)=264V
RMS
•
Line frequency (f
L
) = 60Hz
•
Nominal output power (P
NO
) = 20W (32V/0.625A)
•
Peak output power (P
PO
) = 50W (32V/1.56A)
•
Peak load duration (t
PO
) < 500ms
•
Estimated efficiency:
η
N
= 0.87 and
η
P
= 0.82
P
50
P
INP
=
PO
=
=
61
W
η
P
0.82
P
20
P
INN
=
NO
=
=
23
W
η
N
0.87
FAN6861 can be used for this application because
the peak load duration is less than the OCP delay
time of 780ms.
[STEP-2] Determine the Input Capacitor (C
IN
) and the
Input Voltage Range
[STEP-1] Define the System Specifications
Designing a power supply with peak load current profile,
the following specifications should be determined first:
Line voltage range (V
LINEMIN
and
V
LINEMAX
)
Line frequency (f
L
).
Nominal output power (P
NO
)
Peak output power (P
PO
) and its duration (t
PO
)
Estimated efficiencies for nominal load (η
N
) and peak
load (η
P
): The power conversion efficiency must be
estimated to calculate the input powers for each
condition. Typically, the efficiency at peak load
condition is lower than that of nominal load since most
of the components of power supply are selected for
nominal load condition. If no reference data is available,
set
η
N
= 0.7~0.75 and
η
P
= 0.65~0.7 for low-voltage
output applications and
η
N
= 0.8~0.85 and
η
P
=
0.75~0.8 for high-voltage output applications.
With the estimated efficiency, the input power for peak
load condition is given by:
It is typical to select the input capacitor as 1.5~2μF per watt
of peak input power for universal input range (85-265V
RMS
)
and 0.7~0.8μF per watt of peak input power for European
input range (195V-265V
RMS
). With the input capacitor
chosen, the minimum input capacitor voltage at peak load
condition is obtained as:
V
INP MIN
=
2
⋅
(
V
LINE MIN
)
2
−
P
INP
⋅
(1
−
D
CH
)
C
IN
⋅
f
L
(3)
The minimum input capacitor voltage at nominal load
condition is obtained as:
V
INN MIN
=
2
⋅
(
V
LINE MIN
)
2
−
P
INN
⋅
(1
−
D
CH
)
C
IN
⋅
f
L
(4)
where
D
CH
is the input capacitor charging duty ratio defined
as shown in Figure 2, which is typically about 0.2.
The maximum input capacitor voltage is given as
V
IN MAX
=
2
V
LINE MAX
(5)
P
INP
=
P
PO
η
P
(1)
The input power for nominal load condition is given by:
P
INN
=
P
NO
η
N
(2)
Figure 2. Input Capacitor Voltage Waveform
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 6/9/09
www.fairchildsemi.com
2
AN-6861
APPLICATION NOTE
(Design Example)
By choosing a 100μF capacitor for
the input capacitor, the minimum input voltages for
peak and nominal load are obtained, respectively, as:
V
INP MIN
=
2
⋅
(
V
LINE MIN
)
2
−
=
2
⋅
(90)
2
−
P
INP
⋅
(1
−
D
CH
)
C
IN
⋅
f
L
61
⋅
(1
−
0.2)
=
90
V
100
×
10
−
6
⋅
60
P
INN
⋅
(1
−
D
CH
)
C
IN
⋅
f
L
As can be seen in Equation (7), the voltage stress across the
MOSFET can be reduced by reducing V
RO
. However, this
increases the voltage stresses on the rectifier diodes in the
secondary side. Therefore,
V
RO
should be determined by a
trade-off between the voltage stresses of MOSFET and
diode. Because the actual drain voltage rises above the
nominal MOSFET voltage due to the leakage inductance of
the transformer, as shown in Figure 3, it is typical to set
V
RO
around 70~100V so that
V
DSNOM
is 430~450V for 600V
MOSFET (73~78% of MOSFET voltage rating).
(Design Example)
By determining V
RO
as 100V:
V
INN MIN
=
2
⋅
(
V
LINE MIN
)
2
−
2
23
⋅
(1
−
0.2)
=
2
⋅
(90)
−
=
115
V
100
×
10
−
6
⋅
60
The maximum input voltage is obtained as
V
IN MAX
=
2
⋅
V
LINE MAX
=
2
⋅
264
=
373
V
[STEP-3] Determine the Reflected Output Voltage (V
RO
)
D
MAX
=
V
RO
V
RO
100
=
=
0.53
+
V
INP MIN
100
+
90
V
DS NOM
=
V
IN MAX
+
V
RO
=
273
+
100
=
473
V
When the MOSFET is turned off, the input voltage (V
IN
),
together with the output voltage reflected to the primary,
(V
RO
) are imposed across the MOSFET, as shown in Figure
3. With a given V
RO
, the maximum duty cycle (D
MAX
) and
the maximum nominal MOSFET voltage (V
DSNOM
) are
obtained as:
[STEP-4] Determine
Inductance (L
M
)
the
Transformer
Primary-Side
The transformer primary-side inductance is determined for
the minimum input voltage and peak load condition. With
the D
MAX
from Step-3, the primary-side inductance (L
M
) of
the transformer is obtained as
D
MAX
=
V
RO
V
RO
+
V
INP MIN
(7)
(6)
V
DS NOM
=
V
IN MAX
+
V
RO
(
V
INP MIN
⋅
D
MAX
)
2
L
M
=
2
P
INP
f
SW
K
RF
(8)
where
f
SW
is the switching frequency and
K
RF
is the ripple
factor at peak load and minimum input voltage condition, as
shown in Figure 4.
The ripple factor is closely related to the transformer size
and the RMS value of the MOSFET current. Even though
the conduction loss in the MOSFET can be reduced by
reducing the ripple factor, too small a ripple factor forces an
increase in transformer size. From practical point of view, it
is reasonable to set
K
RF
= 0.3~0.6 for the universal input
range and
K
RF
= 0.4~0.8 for the European input range.
Once
L
M
is calculated by determining K
RF
from Equation
(8), the peak current and RMS current of the MOSFET for
minimum input voltage and peak load condition are
obtained as:
I
DS
PK
=
I
EDC
+
Δ
I
2
(9)
(10)
(11)
(12)
www.fairchildsemi.com
Δ
I
⎤
D
⎡
I
DS RMS
= ⎢
3(
I
EDC
)
2
+
( )
2
⎥
MAX
2
⎦
3
⎣
P
INP
where:
I
EDC
=
V
INP MIN
⋅
D
MAX
Figure 3. The Output Voltage Reflected to the
Primary
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 6/9/09
and
V
INP MIN
D
MAX
Δ
I
=
L
M
f
SW
3
AN-6861
APPLICATION NOTE
K
RF
Δ
I
Δ
I
=
2
I
EDC
The peak drain current at minimum input voltage and peak
load condition was obtained from Equation (9) in Step-4.
The peak drain current at minimum input voltage and
nominal load condition is given as:
I
DS
.
N
PK
P
INN
⋅
(
V
IN MIN
+
V
RO
)
=
V
INN MIN
⋅
V
RO
+
V
INN MIN
⋅
V
RO
2
L
M
f
SW
⋅
(
V
INN MIN
+
V
RO
)
:
CCM
(13)
I
D
S
PK
Figure 4. MOSFET Current and Ripple Factor (K
RF
)
I
DS
.
N PK
=
2
⋅
P
INN
f
SW
⋅
L
M
:
DCM
(14)
(Design Example)
Determining the ripple factor as 0.57
L
M
=
(
V
INP
⋅
D
MAX
)
(90
⋅
0.53)
=
2
P
INP
f
SW
K
RF
2
⋅
61
⋅
65
×
10
3
⋅
0.57
MIN
2
2
Whether the converter operates in CCM or DCM at
minimum input voltage and nominal load condition is
determined by:
=
503
μ
H
I
EDC
P
INP
61
=
=
=
1.28
A
MIN
V
INP
⋅
D
MAX
90
⋅
0.53
2
P
INN
L
M
f
SW
(
V
INN MIN
+
V
RO
)
⋅
>
1 :
CCM
V
INN MIN
⋅
V
RO
+
V
RO
)
(
V
INN
<
1 :
DCM
V
INN MIN
⋅
V
RO
MIN
(15)
Δ
I
=
V
INP
D
MAX
90
⋅
0.53
=
=
1.46
A
L
M
f
SW
503
×
10
−
6
⋅
65
×
10
3
MIN
2
P
INN
L
M
f
SW
⋅
I
DS
PK
=
I
EDC
+
Δ
I
=
1.28
+
0.73
=
2.01
A
2
The condition for the sensing resistor is given as:
I
DS RMS
Δ
I
⎤
D
⎡
= ⎢
3(
I
EDC
)
2
+
( )
2
⎥
MAX
2
⎦
3
⎣
R
CS
<
R
CS
<
0.5
I
DS
.
N PK
0.89
I
DS PK
(16)
0.53
⎡
⎤
= ⎣
3(1.28)
2
+
(0.73)
2
⎦
=
0.98
A
3
[STEP-5] Determine the Sensing Resistor Value
(Design Example)
For minimum input voltage and
nominal load condition, the operation mode is DCM as:
The current sensing resistor value should be determined
considering the over-current protection threshold and the
pulse-by-pulse current limit threshold, as shown in Figure 5.
The peak value of current sensing voltage (V
CS
) should be
lower than the pulse-by-pulse current limit level for peak
load condition. It should be lower than the OCP threshold
for nominal load conditions to prevent false triggering of
OCP protection during normal operation.
2
P
INN
L
M
f
SW
(
V
INN MIN
+
V
RO
)
⋅
V
INN MIN
⋅
V
RO
(115
+
100)
<
1
115
⋅
100
=
2
⋅
23
⋅
503
×
10
−
6
⋅
65
×
10
3
⋅
The peak drain current at minimum input voltage and
nominal power condition is given as:
I
DS.N
PK
=
2
⋅
P
INN
=
f
SW
⋅
L
M
2
⋅
23
=
1.19
A
65
×
10
3
⋅
503
×
10
−
6
The conditions for the sensing resistor are given as:
R
CS
<
V
CS
=
I
DS
⋅
R
CS
0.5
I
DS
.
N PK
0.89
I
DS
.
P
2
PK
=
0.5
=
0.42
Ω
1.19
0.89
=
0.44
Ω
2.01
R
CS
<
=
Figure 5. Determining Current Sensing Resistor
Thus, a 0.39Ω resistor is selected for the current-sensing
resistor
www.fairchildsemi.com
4
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 6/9/09
AN-6861
APPLICATION NOTE
[STEP-6] Determine the Minimum Primary Turns
With a given core, the minimum number of turns for the
transformer primary side to avoid the core saturation is
given by:
[STEP-7] Determine the Number of Turns for Each
Winding
N
P
min
=
where
A
e
is the cross-sectional area of the core in mm
2
, I
LIM
is the pulse-by-pulse current limit level determined by
0.89V threshold, R
CS
is current sensing resistor, and
B
SAT
is
the saturation flux density in Tesla.
The pulse-by-pulse current limit level is included in
Equation (17) because the inductor current reaches the
pulse-by-pulse current limit level during the load transient
or overload condition. Figure 6 shows the typical
characteristics of ferrite core from TDK (PC40). Since the
saturation flux density (B
SAT
) decreases as the temperature
goes high, the high temperature characteristics should be
considered. If there is no reference data, use
B
MAX
=0.3T.
L
⋅
0.89 /
R
CS
L
M
I
LIM
×
10
6
=
M
×
10
6
B
SAT
A
e
B
SAT
A
e
(17)
Figure 7 shows a simplified diagram of the transformer.
First, calculate the turn ratio (n) between the primary side
and the secondary side from the reflected output voltage
determined in Step-3, as:
n
=
V
RO
N
P
=
N
S
V
O
+
V
F
(18)
where
N
P
and
N
S
are the number of turns for primary side
and secondary side, respectively,
V
O
is the output voltage;
and
V
F
is the diode (D
O
) forward-voltage drop. Then,
determine the proper integer for
N
S
such that the resulting
N
P
is larger than
N
Pmin
obtained from Equation (17).
The number of turns for the auxiliary winding for V
DD
supply is determined as:
V
DD
*
+
V
F
N
A
=
⋅
N
S
1
V
O
+
V
FA
(19
)
where
V
DD
is the nominal value of the supply voltage and
V
FA
is the forward voltage drop of
D
DD
as defined in Figure
7. Since V
DD
increases as the output load increases, it is
proper to set
V
DD
at 3~5V higher than V
DD
UVLO level
(9.5V) to avoid the over-voltage protection condition during
the peak load operation.
Figure 6. Typical B-H Characteristics of Ferrite Core
(TDK/PC40)
Figure 7. Simplified Transformer Diagram
(Design Example)
A
EF25/13/11 core is selected,
(Design Example)
Assuming the diode forward-
whose effective cross-sectional area is 78mm .
Choosing the saturation flux density as 0.25T, the
minimum number of turns for the primary side is
obtained as:
L
⋅
0.89 /
R
CS
N
P
min
=
M
×
10
6
B
SAT
A
e
2
503
×
10
−
6
⋅
0.89 / 0.39
=
×
10
6
=
59
0.25
⋅
78
voltage drop is 1V, the turn ratio is obtained as:
V
RO
N
100
n
=
P
=
=
=
3.03
N
S
V
O
+
V
F
32
+
1
Then, determine the proper integer for
N
S
such that the
resulting
N
P
is larger than
N
Pmin
as:
N
S
=
20,
N
P
=
n
⋅
N
S
=
61
>
N
P
min
Setting V
DD
* as 12.5V, the number of turns for the
auxiliary winding is obtained as:
V
DD
*
+
V
F
12.5
+
1
⋅
N
S
=
⋅
20
=
8
N
A
=
32
+
1
V
O
+
V
FA
www.fairchildsemi.com
5
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 6/9/09
京公网安备 11010802033920号
EEWORLD
