FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
April 2011
FAN6920MR
Integrated Critical-Mode PFC and Quasi-Resonant
Current-Mode PWM Controller
Features
Integrated PFC and Flyback Controller
Critical-Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal Minimum 5µs t
OFF
for QR PWM Stage
Internal 5ms Soft-Start for PWM
Brownout Protection
High / Low Line Over-Power Compensation
Auto-Recovery Over-Current Protection
Auto-Recovery Open-Loop Protection
Externally Auto-Recovery Triggering (RT Pin)
Adjustable Over-Temperature Protection
VDD Pin and Output Voltage OVP (Auto-Recovery)
Internal Over-Temperature Shutdown (140°C)
Description
The highly integrated FAN6920MR combines Power
Factor Correction (PFC) controller and quasi-resonant
PWM controller. Integration provides cost-effective
design and reduces external components.
For PFC, FAN6920MR uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power-factor correction. With an
innovative THD optimizer, FAN6920MR can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6920MR provides several functions to
enhance the power system performance: valley
detection, green-mode operation, and high / low line
over-power compensation. Protection functions include
secondary-side open-loop and over-current with auto-
recovery protection; external auto-recovery triggering;
adjustable over-temperature protection by RT pin; and
external NTC resistor, internal over-temperature
shutdown, V
DD
pin OVP, and DET pin over-voltage for
output OVP, and brown-in / out for AC input voltage
UVP.
The FAN6920MR controller is available in a 16-pin
small-outline package (SOP).
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Ordering Information
Part Number
FAN6920MRMY
OLP Mode
Recovery
Operating
Temperature Range
-40°C to +105°C
Package
16-Pin Small Outline Package (SOP)
Packing
Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
www.fairchildsemi.com
FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller
Application Diagram
Figure 1. Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
www.fairchildsemi.com
2
FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller
Internal Block Diagram
COMP
HV
VDD
2
RANGE
2.65V
2.75V
Multi-Vector Amp.
2.75V
2.9V
2.3V
V
COMP-H
0.45V
V
COMP-L
RANGE
16
OVP
I
HV
27.5V
Auto-Recovery
UVP
Debounce
70µs
OVP
7
Internal
Bias
Two-Step
UVLO
12V/7V/5V
DRV
15
NC
S
Auto-
Recovery
Brownout
Sawtooth
Generator
t
on-max
SET
Q
15.5V
6
OPFC
I
COMP-BURST
COMP-L
INV
3
2.5V
COMP-H
R
CLR
Q
Restarter
PFC Zero-Current
Detector
Disable
Function
0.2V
Inhibit
Timer
2.1V/1.75V
THD
Optimizer
PFC
Current Limit
CSPFC
4
0.82V
Blanking
Circuit
V
COMP-H
COMP-H
COMP-L
V
CTRL-PFC
5V
4.2V
2R
2.25ms
28µs
R
Debounce
PFC Burst Mode
V
IN
V
INV
Auto-Recovery
Timer
50ms
VB
FB OLP
Starter
0.7V
I
ZCD
14
10V
ZCD
FB
11
Soft-Start
5ms
2.3V/0.8V
V
INV
PWM-ON/OFF
CSPWM
5
Blanking
Circuit
PWM
Current Limit
I
DET
Auto-Recovery
t
OFF-MIN
(5µs/20.5µs/2.25ms)
I
DET
Valley
Detector
(30µA)
Brownout
Protection
DRV
S
SET
Q
17.5V
8
OPWM
Over-Power
Compensation
R
CLR
Q
(RT Pin) Prog. OTP
(RT Pin) Externally Triggering
DET Pin OVP
VDD Pin OVP
Internal OTP
Startup
V
B
& Clamp
V
comp
to 1.6V
Debounce
100mS
Brownout
Comparator
PFC RANGE Control
Debounce
2.4V/2.25V
Auto-
Recovery
Protection
1st
Valley
t
OFF-MIN
+9µs
Auto-Recovery
t
OFF
Blanking
(2.5µs)
S/H
V
DET
Auto-Recovery
2.5V
DET OVP
I
RT
1
RANGE
Debounce
Time
1.2V
V
INV
1V/1.2V
100µs
10ms
DET
10
5V
I
DET
100µA
0.7V
0.8V
Internal
OTP
Auto-Recovery
0.5V
Prog. OTP
/ Externally Triggering
9
GND
12
RT
13
VIN
PFC Burst Mode
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
www.fairchildsemi.com
3
FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller
Marking Information
16
ZXYTT
FAN6920FO
TPM
1
- Fairchild Logo
Z -
Plant Code
X -
Year Code
Y -
Week Code
TT -
Die Run Code
F -
Frequency (M = Low, H = High Level)
O -
OLP Mode (L = Latch, R = Recovery)
T -
Package Type (M = SOP)
P -
Y = Green Compound
M -
Manufacturing Flow Code
Figure 3. Marking Diagram
Pin Configuration
RANGE
COMP
INV
CSPFC
CSPWM
OPFC
VDD
OPWM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HV
N.C.
ZCD
VIN
RT
FB
DET
GND
Figure 4. Pin Configuration
Pin Definitions
Pin #
1
Name Description
The RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage
RANGE detected by the VIN pin is higher than a threshold voltage, it sets to low impedance; whereas it
sets to high impedance if input voltage is at a high level.
COMP
Output pin of the error amplifier. It is a transconductance-type error amplifier for PFC output
voltage feedback. Proprietary multi-vector current is built-in to this amplifier; therefore, the
compensation for PFC voltage feedback loop allows a simple compensation circuit between this
pin and GND.
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
divider and provides PFC output over- and under-voltage protections. This pin also controls the
PWM startup. Once the FAN6920MR is turned on and V
INV
exceeds in 2.3V, PWM starts.
2
3
INV
4
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
CSPFC protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal
threshold (0.82V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
during PWM t
ON
time.
Continued on the following page…
5
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
www.fairchildsemi.com
4
FAN6920MR — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode Flyback PWM Controller
Pin Definitions
(Continued)
Pin #
6
7
8
9
Name
OPFC
VDD
OPWM
GND
Description
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
is 15.5V.
Power supply. The threshold voltages for startup and turn-off are 12V and 7V, respectively. The
startup current is less than 30µA and the operating current is lower than 10mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5V.
The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
Producing an offset voltage to compensate the threshold voltage of PWM current limit for over-
power compensation. The offset is generated in accordance with the input voltage when the
PWM switch is on.
Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
Providing output over-voltage protection. A voltage comparator is built in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
over voltage and this flat voltage are higher than 2.5V, the controller stops all PFC and PWM
switching operation. The protection mode is auto-recovery.
Feedback voltage pin used to receive the output voltage level signal to determine PWM gate duty
for regulating output voltage. The FB pin voltage can also activate open-loop, overload protection
and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2V
for more than 50ms.The input impedance of this pin is a 5kΩequivalent resistance. A 1/3
attenuator is connected between the FB pin and the input of the CSPWM/FB comparator.
Adjustable over-temperature protection and external protection triggering. A constant current
flows out from the RT pin. When RT pin voltage is lower than 0.8V (typical), protection is
activated and stops PFC and PWM switching operation. This protection is auto-recovery.
Line-voltage detection for brownin / out protections. This pin can receive the AC input voltage
level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status, but it can also perform brownin / out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching
cycle. When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and
the controller stops PFC switching. This can be realized with an external circuit if disabling the
PFC stage is desired.
No connection
High-voltage startup pin is connected to the AC line voltage through a resistor (100kΩtypical) for
providing a high charging current to V
DD
capacitor.
10
DET
11
FB
12
RT
13
VIN
14
ZCD
15
16
NC
HV
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
www.fairchildsemi.com
5
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