MT8977AP datasheet, PDF - EEWORLD Datasheet

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MT8977AP: DescriptionDATACOM, FRAMER, PQCC44, PLASTIC, MS-018AC, LCC-44; CategoryWireless rf/communication Telecom circuit; File Size1MB，36 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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MT8977AP Overview

DATACOM, FRAMER, PQCC44, PLASTIC, MS-018AC, LCC-44

MT8977AP Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	LPCC
package instruction	PLASTIC, MS-018AC, LCC-44
Contacts	44
Reach Compliance Code	unknown
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.585 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
Certification status	COMMERCIAL
Maximum seat height	4.57 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.585 mm

MT8977AP Preview

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MT8977



T1/ESF Framer Circuit (ACCUNET T1.5)

Data Sheet

Features

•

D3/D4 or ESF framing and SLC-96 compatible

Two frame elastic buffer with jitter tolerance

improved to 156 UI

Insertion and detection of A, B, C, D bits,

signalling freeze, optional debounce

Selectable B8ZS, jammed bit (ZCS) or no zero

code suppression

Yellow alarm and blue alarm signal capabilities

Bipolar violation count, F

error count, CRC error

count

Selectable robbed bit signalling

Frame and superframe sync. signals, Tx and Rx

AMI encoding and decoding

Per channel, overall, and remote loop around

Digital phase detector between T1 line and ST-

BUS

One uncommitted scan point and drive point

Pin compatible with MT8976 and MT8979

ST-BUS compatible

Ordering Information

MT8977AE

28 Pin PDIP

MT8977AP

44 Pin PLCC

MT8977APR

44 Pin PLCC

MT8977AP1

44 Pin PLCC*

MT8977APR1

44 Pin PLCC*

MT8977AE1

28 Pin PDIP*

*Pb Free Matte Tin

-40°C to +85°C

September 2005

ISO CMOS ST-BUS

Family

Tubes

Tape & Reel

Tubes

Tape & Reel

Tubes

Applications

•

DS1/ESF digital trunk interfaces

Computer to PBX interfaces (DMI and CPI)

High speed computer to computer data links

Description

The MT8977 is a variant of the MT8976 framer, which

has been enhanced to meet ACCUNET T1.5 wander

tolerance (138 UI).

The MT8977 meets ESF and D3/D4 formats, and is

compatible with SLC-96 systems.

TxSF

C2i

F0i

RxSF

DSTo

DSTi

C1.5i

ST-BUS

Timing

Circuitry

2 Frame

Elastic Buffer

with Slip

Control

DS1

Link

Interface

2048-1544

Converter

RxFDLClk

RxFDL

RxA

Remote &

Digital

Loopbacks

RxB

TxA

TxB

TxFDLClk

TxFDL

RxD

Serial

Control

Interface

ABCD

Signalling RAM

E1.5i

Phase

Detector

DS1

Counter

Data

Interface

CSTi0

CSTi1

CSTo

XCtl

XSt

Control Logic

•

E8Ko

Figure 1 - Functional Block Diagram

ACCUNET

T1.5 is a registered trademark of AT & T

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT8977

VSS

DSTo

TxB

TxA

VDD

F0i

E1.5i

Data Sheet

28 PIN PDIP

Figure 2 - Pin Connections

Pin Description

Pin #

DIP

PLCC

Name

TxA

TxB

DSTo

RxA

Description

Transmit A Output.

Unipolar output that can be used in conjunction with TxB and

external line driver circuitry to generate the bipolar DS1 signal.

Transmit B Output.

Unipolar output that can be used in conjunction with TxA and

external line driver circuitry to generate the bipolar DS1 signal.

Data ST-BUS Output.

A 2048 kbit/s serial output stream which contains the 24 PCM or

data channels received from the DS1 line.

No Connection.

Receive A Complementary Input.

Accepts a unipolar split phase signal decoded

externally from the received DS1 bipolar signal. This input, in conjunction with RxB,

detects bipolar violations in the received signal.

Receive B Complementary Input.

Accepts a unipolar split phase signal decoded

externally from the received DS1 bipolar signal. This input, in conjunction with RxA,

detects bipolar violations in the received signal.

Receive Data Input.

Unipolar RZ data signal decoded from the received DS1 signal.

Generally the signals input at RxA and RxB are combined externally with a NAND gate

and the resulting composite signal is input at this pin.

Control ST-BUS Input #1.

channel control words.

A 2048 kbit/s serial control stream which carries 24 per-

RxB

RxD

CSTi1

TxFDL

Transmit Facility Data Link (Input).

A 4 kHz serial input stream that is multiplexed into

the FDL position in the ESF mode, or the F

pattern when in SLC-96 mode. It is clocked

in on the rising edge of TxFDLClk.

Zarlink Semiconductor Inc.

VSS

CSTi0

E8Ko

VSS

XCtl

XSt

CSTo

RxFDLClk

DSTi

44 PIN PLCC

TxA

TxB

DSTo

RxA

RxB

RxD

CSTi1

TxFDL

TxFDLClk

CSTi0

E8Ko

VSS

VDD

F0i

E1.5i

C1.5i

RxSF

TxSF

C2i

RxFDL

DSTi

RxFDLClk

CSTo

XSt

XCtl

RxA

RxB

RxD

CSTi1

TxFDL

TxFDLClk

6 5 4 3 2 1 44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

C1.5i

RxSF

TxSF

C2i

RxFDL

MT8977

Pin Description (continued)

Pin #

DIP

PLCC

Data Sheet

Name

TxFDLClk

Description

Transmit Facility Data Link Clock (Output).

A 4 kHz clock used to clock in the FDL

data.

No connection.

Control ST-BUS Input #0.

A 2048 kbit/s serial control stream that contains 24 per channel

control words and two master control words.

Extracted 8 kHz Output.

The E1.5i clock is internally divided by 193 to produce an 8 kHz

clock which is aligned with the received DS1 frame and output at this pin. The 8 kHz signal

is derived from C1.5 in Digital Loopback mode.

System Ground.

External Control (Output).

This is an uncommitted external output pin which is set or reset

via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per frame.

External Status (Schmitt Trigger Input).

The state of this pin is sampled once per frame

and the status is reported in bit 5 of Master Status Word 2 on CSTo.

Control ST-BUS Output.

This is a 2048 kbit/s serial control stream which provides the 24

per-channel status words, and two master status words.

Receive Facility Data Link Clock (Output).

A 4 kHz clock signal used to clock out FDL

information. The data is clocked out on the rising edge of RxFDLClk.

Data ST-BUS Input.

This pin accepts a 2048 kbit/s serial stream which contains the 24 PCM

or data channels to be transmitted on the T1 trunk.

Received Facility Data Link (Output).

A 4 kHz serial output stream that is demultiplexed

from the FDL in ESF mode, or the received Fs bit pattern in SLC-96 mode. It is clocked out

on the rising edge of RxFDLClk.

2.048 MHz Clock Input.

This is the master clock used for clocking serial data into DSTi,

CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.

Transmit Superframe Pulse Input.

A low going pulse applied at this pin will make the next

transmit frame the first frame of a superframe. The device will free run if this pin is held

high.

Received Superframe Pulse Output.

A pulse output on this pin designates that the next

frame of data on the ST-BUS is from frame 1 of the received superframe. The period is 12

frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are output only when the

device is synchronized to the received DS1 signal.

1.544 MHz Clock Input.

This is the DS1 transmit clock and is used to output data on TxA

and TxB. It must be phase-locked to C2i. Data is clocked out on the rising edge of C1.5i.

1.544 MHz Extracted Clock (Input).

This clock which is extracted from the received data

is used to clock in data at RxA, RxB and RxD. The falling edge of the clock is nominally

aligned with the center of the received bit on RxD, RxA and RxB.

Frame Pulse Input.

This is the frame synchronization signal which defines the beginning of

the 32 channel ST-BUS frame.

Internal Connection.

Tied to V

for normal operation

CSTi0

E8Ko

6, 18,

XCtl

XSt

CSTo

RxFDLClk

DSTi

RxFDL

C2i

TxSF

RxSF

C1.5i

E1.5i

F0i

Zarlink Semiconductor Inc.

MT8977

Pin Description (continued)

Pin #

DIP

PLCC

Data Sheet

Name

Description

Positive Power Supply Input.

+5V

±5%.

Functional Timing Diagrams

125µSec

C2i

DSTi

DSTo

CSTi0/CSTi1

•

CSTo

•

Figure 3 - ST-BUS Timing

125µSec

E1.5i

INT DATA

DS1 AMI

LINE SIGNAL

RxA

RxB

RxD

E8Ko

Figure 4 - FiDS1 Receive Timing

Zarlink Semiconductor Inc.

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

MT8977AP Related Products

	MT8977AP	MT8977APR
Description	DATACOM, FRAMER, PQCC44, PLASTIC, MS-018AC, LCC-44	DATACOM, FRAMER, PQCC44, PLASTIC, MS-018AC, LCC-44
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	Rochester Electronics	Rochester Electronics
Parts packaging code	LPCC	LPCC
package instruction	PLASTIC, MS-018AC, LCC-44	PLASTIC, MS-018AC, LCC-44
Contacts	44	44
Reach Compliance Code	unknown	unknown
JESD-30 code	S-PQCC-J44	S-PQCC-J44
JESD-609 code	e0	e0
length	16.585 mm	16.585 mm
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	44	44
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225	225
Certification status	COMMERCIAL	COMMERCIAL
Maximum seat height	4.57 mm	4.57 mm
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Telecom integrated circuit types	FRAMER	FRAMER
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN LEAD	TIN LEAD
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	16.585 mm	16.585 mm

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