TIBPAL16R4-10C, 'R6-10C, 'R6-12M, 'L8-12M are Not Recommended for New Designs. TIBPAL16R8-10C, 'R8-12M are Obsolete.
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
•
High-Performance Operation:
f
max
(w/o feedback)
TIBPAL16R’-10C Series . . . 62.5 MHz Min
TIBPAL16R’-12M Series . . . 56 MHz Min
f
max
(with feedback)
TIBPAL16R’-10C Series . . . 55.5 MHz Min
TIBPAL16R’-12M Series . . . 48 MHz Min
Propagation Delay
TIBPAL16L’-10C Series . . . 10 ns Max
TIBPAL16L’-12M Series . . . 12 ns Max
Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
Preload Capability on Output Registers
Simplifies Testing
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Security Fuse Prevents Duplication
Dependable Texas Instruments Quality and
Reliability
DEVICE
PAL16L8
PAL16R4
PAL16R6
PAL16R8
I
INPUTS
10
8
8
8
3-STATE
O OUTPUTS
2
0
0
0
REGISTERED
Q OUTPUTS
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
I/O
PORT
S
6
4
2
0
SRPS017A
−
D3023, MAY 1987
−
REVISED DECEMBER 2010
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
•
•
•
•
•
•
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
VCC
O
I
I
I
I
I
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I/O
I/O
I/O
I/O
I/O
description
Pin assignments in operating mode
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
All of the register outputs are set to a low level during power up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of
−55°C
to 125°C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2010, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
I
GND
I
O
I/O
1
TIBPAL16R4-10C, 'R6-10C, 'R6-12M, 'L8-12M are Not Recommended for New Designs. TIBPAL16R8-10C, 'R8-12M are Obsolete.
SRPS017A
−
D3023, MAY 1987
−
REVISED DECEMBER 2010
TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
10
11
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
10
11
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
10
11
Pin assignments in operating mode
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
I
GND
CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
V
CC
Q
Q
Q
Q
Q
Q
Q
Q
OE
I
I
CLK
VCC
Q
I
I
I
I
I
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I
GND
CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
V
CC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
I
I
CLK
VCC
I/O
I
I
I
I
I
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I
GND
CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
V
CC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
I
I
CLK
VCC
I/O
I
I
I
I
I
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I/O
Q
Q
Q
Q
OE
I/O
I/O
Q
Q
Q
Q
Q
OE
I/O
Q
Q
Q
Q
Q
Q
OE
Q
Q