GS8152Z18B-150I datasheet, PDF

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GS8152Z18B-150I: DescriptionZBT SRAM, 1MX18, 10ns, CMOS, PBGA119; Categorystorage storage; File Size757KB，39 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8152Z18B-150I Overview

ZBT SRAM, 1MX18, 10ns, CMOS, PBGA119

GS8152Z18B-150I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
package instruction	BGA, BGA119,7X17,50
Reach Compliance Code	compliant
Maximum access time	10 ns
Maximum clock frequency (fCLK)	150 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
memory density	18874368 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum standby current	0.02 A
Minimum standby current	3.14 V
Maximum slew rate	0.233 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM

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Preliminary

GS8152Z18/36/72B-225/200/180/166/150/133

119 and 209 BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119- or 209-Bump BGA package

-225 -200 -180 -166

Flow

7.0 7.5 8.0 8.5

8.5 10.0 10.0 10.0

Through

tCycle

2-1-1-1 Curr (x18) 205 185 185 185

Curr (x36) 240 210 210 210

Curr (x72) 325 285 285 285

2.5 3.0 3.2 3.5

Pipeline

4.4 5.0 5.5 6.0

3-1-1-1

tCycle

Curr (x18) 350 315 290 270

Curr (x36) 410 370 340 315

Curr (x72) 570 515 470 435

-150

10.0

185

210

285

3.8

6.7

250

290

400

-133

11.0

15.0

140

160

205

4.0

7.5

230

260

360

Unit

16Mb Pipelined and Flow Through

225MHz–133MHz

3.3 V V

Synchronous NBT SRAM

2.5 V or 3.3 V I/O

Functional Description

The GS8152Z18/36/72B is a 16Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8152Z18/36/72B may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8152Z18/36/72B is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 119-bump (x18 & x36) or 209-bump (x72) BGA

package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Rev: 1.01 11/2000

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1/39

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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