IDTQS5LV931-80Q datasheet, PDF

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IDTQS5LV931-80Q: DescriptionPLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20; Categorylogic logic; File Size73KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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IDTQS5LV931-80Q Overview

PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20

IDTQS5LV931-80Q Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QSOP
package instruction	QSOP-20
Contacts	20
Reach Compliance Code	not_compliant
series	5LV
Input adjustment	SCHMITT TRIGGER
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	8.65 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	6
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
propagation delay (tpd)	0.5 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.3 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9116 mm
minfmax	80 MHz

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QS5LV931

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

INDUSTRIAL TEMPERATURE RANGE

3.3V LOW SKEW CMOS PLL

CLOCK DRIVER WITH

INTEGRATED LOOP FILTER

FEATURES:

•

3.3V operation

JEDEC LVTTL compatible level

Clock input is 5V tolerant

Q outputs, Q/2 output

<300ps output skew, Q

–Q

Outputs 3-state and reset while OE/RST low

PLL disable feature for low frequency testing

Internal loop filter RC network

Internal VCO/2 option

Balanced drive outputs ±24mA

ESD >2000V

80MHz maximum frequency

Available in QSOP package

QS5LV931

DESCRIPTION:

The QS5LV931 Clock Driver uses an internal phase locked loop

(PLL) to lock low skew outputs to a reference clock input. Six outputs

are available: Q

–Q

, Q/2. Careful layout and design ensure <300ps

skew between the Q

–Q

, and Q/2 outputs. The QS5LV931 includes

an internal RC filter which provides excellent jitter characteristics and

eliminates the need for external components. Various combinations of

feedback and a divide-by-2 in the VCO path allow applications to be

customized for linear VCO operation over a wide range of input SYNC

frequencies. The PLL can also be disabled by the PLL_EN signal to

allow low frequency or DC testing. The QS5LV931 is designed for use

in cost sensitive high-performance computing systems, workstations,

multi-board computers, networking hardware, and mainframe systems.

Several can be used in parallel or scattered throughout a system for

guaranteed low skew, system-wide clock distribution networks. In the

QSOP package, the QS5LV931 clock driver represents the best value

in small form factor, high-performance clock management products.

For more information on PLL clock driver products, see Application

Note AN-227.

FUNCTIONAL BLOCK DIAGRAM

FEEDBACK

PLL_EN

FREQ_SEL

SYNC

O E/RST

PH ASE

DETE CTO R

LOO P

FILTER

VCO

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

2002

Integrated Device Technology, Inc.

JANUARY 2002

DSC-5821/4

IDTQS5LV931-80Q Related Products

	IDTQS5LV931-80Q	IDTQS5LV931-50Q	QS5LV931-66QG	IDTQS5LV931-66Q	QS5LV931-80QG	QS5LV931-50QG
Description	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, GREEN, QSOP-20	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, GREEN, QSOP-20	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, GREEN, QSOP-20
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QSOP	QSOP	QSOP	QSOP	QSOP	QSOP
package instruction	QSOP-20	QSOP-20	GREEN, QSOP-20	QSOP-20	SSOP,	SSOP,
Contacts	20	20	20	20	20	20
Reach Compliance Code	not_compliant	not_compliant	compliant	not_compliant	unknown	unknown
series	5LV	5LV	5LV	5LV	5LV	5LV
Input adjustment	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER	SCHMITT TRIGGER
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e0	e0	e3	e0	e3	e3
length	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1	1	1
Number of terminals	20	20	20	20	20	20
Actual output times	6	6	6	6	6	6
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP	SSOP	SSOP	SSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
propagation delay (tpd)	0.5 ns	0.5 ns	0.5 ns	0.5 ns	0.5 ns	0.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.3 ns	0.3 ns	0.3 ns	0.3 ns	0.3 ns	0.3 ns
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	MATTE TIN	Tin/Lead (Sn85Pb15)	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	3.9116 mm	3.9116 mm	3.9116 mm	3.9116 mm	3.9116 mm	3.9116 mm
minfmax	80 MHz	50 MHz	66 MHz	66 MHz	80 MHz	50 MHz
Is it Rohs certified?	incompatible	incompatible	conform to	incompatible	-	-
Peak Reflow Temperature (Celsius)	240	240	260	225	-	-
Maximum time at peak reflow temperature	30	30	30	30	-	-

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