R5109G Series
Watchdog Timer Equipped with 2-Clock Monitoring with VD
The R5109G Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single chip.
R5109G monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset signal when a
malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted with an external capacitor
with a high degree of accuracy. R5109G is equipped with the function that inhibits clock monitoring of the WDT (INH) and the function to
supervise two different clocks.
FEATURES
•
Supply Current (I
SS
) ························Typ. 11.5μA (V
DD
=-V
DET
+0.5V,
•
Operating Voltage Range (V
DD
) ······0.9V to 6.0V
Clock pulse input)
•
Output Delay Time (t
PLH
)················· Typ. 370ms (C
D
=0.1μF)
•
Output Delay Time Accuracy ··········
±
16% (-40°C
<
Topt
<
105°C)
=
=
(WDT Section)
•
Watchdog Timeout Period (t
WD
) ······ Typ. 310ms (C
TW
=0.1μF)
(VD Section)
•
Detector Threshold Range (-V
DET
)·····1.5V to 5.5V (internally fixed)
•
Reset Hold Time of WDT (t
WR
) ······· Typ. 34ms (C
TW
=0.1μF)
•
Detector Threshold Accuracy ·········± 1%
•
Watchdog Timeout Period Accuracy ····
±
33% (-40°C
<
Topt
<
105°C)
=
=
•
Temp. coeff. of Detector Threshold ···Typ.
±
100ppm/°C
•
Package ········································· SSOP-8G
(The above shows specification at Topt=25
°
C. Design assurance value at -40
°
C
<
Topt
<
105
°
C is also available. For details, please refer to the datasheet.)
=
=
BLOCK DIAGRAMS
R5109Gxx1A
(Nch. open drain output)
V
DD
V
DD
TYPICAL APPLICATION
R5109Gxx1C
(CMOS output)
Power Supply
R
Microprocessor 1
V
DD
RESET
I/O
Microprocessor 2
C
TW
V
DD
RESET
8
V
DD
C
D
Vref2
Vref1
RESETB
1
SCK1
5
R5109Gxx1A
Series
SCK2
6
GND
C
TW
7
C
D
Vref2
Vref1
2
INH
GND
GND
C
TW
WATCHDOG
TIMER
CLOCK
DETECTOR
CLOCK
DETECTOR
C
TW
SCK1
SCK2
WATCHDOG
TIMER
CLOCK
DETECTOR
CLOCK
DETECTOR
3
C
D
SCK1
SCK2
SW
C
D
4
I/O
RESETB
INH
RESETB
INH
SELECTION GUIDE
Package
SSOP-8G
Quantity per Reel
3,000 pcs
Part No.
R5109G
.xx.1.
∗
-TR-F
.xx.
: Specify the detector threshold within the range 1.5V (.15.) to 5.5V (.55.)
in 0.1V steps.
.∗
: Select the output type from (.A.) Nch. open drain or (.C.) CMOS.
PACKAGE (Top View)
SSOP-8G
8 7 6 5
TIMING CHART
DET
V
DD
+V
DET
-V
V
INH
t
PHL
t
PHL
t
PHL
1
2
3
4
V
CD
+V
TCD
-V
TCD
t
WD
V
ref2H
t
WDI
1
2
3
4
5
6
7
8
RESETB
INH
C
D
GND
SCK1
SCK2
C
TW
V
DD
Output pin for Reset "L" signal
Inhibit pin
Ext. Cap. pin for setting output
delay time of VD
Ground pin
Watchdog timer clock input pin 1
Watchdog timer clock input pin 2
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
Power supply pin
V
CTW
V
ref2L
V
SCK1
V
SCK2
t
PLH
t
WR
t
PLH
t
PLH
V
RESETB
APPLICATION
•
Monitoring of the power system of devices equipped with microprocessors
∗t
PHL
: Output delay time
∗t
WDI
: t
WD
/10 (SCK pulses input during this period are ignored.)
No.EK-172-091101
CMOS Microprocessor Supervisory
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