M395T5160CZ4-CD56 datasheet, PDF

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M395T5160CZ4-CD56: DescriptionDDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, FBDIMM-240; Categorystorage storage; File Size542KB，28 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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M395T5160CZ4-CD56 Overview

DDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, FBDIMM-240

M395T5160CZ4-CD56 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
I/O type	COMMON
JESD-30 code	R-XDMA-N240
memory density	38654705664 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,1.8 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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FBDIMM

DDR2 SDRAM

DDR2 Fully Buffered DIMM

240pin FBDIMMs based on 1Gb C-die

60FBGA with Lead-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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Rev. 1.52 April 2008

FBDIMM

Table of Contents

DDR2 SDRAM

1.0 FEATURES .....................................................................................................................................4

2.0 FBDIMM GENERALS .....................................................................................................................5

2.1 FB-DIMM Operation Overview

..........................................................................................................5

2.2 FB-DIMM Channel Frequency Scaling

...............................................................................................6

2.3 FB-DIMM Clocking Scheme

.............................................................................................................7

2.4 FB-DIMM Protocol

..........................................................................................................................7

2.5 Southbound Command Delivery

......................................................................................................8

2.6 Basic Timing Diagram

.....................................................................................................................9

2.7 Advanced Memory Buffer Block Diagram

........................................................................................11

2.8 Interfaces

....................................................................................................................................12

3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE ...............12

3.1 DDR2 Channel

.............................................................................................................................12

..................................................................................................................12

3.3 FBD Channel Latency

...................................................................................................................13

3.4 Peak Theoretical Throughput

.........................................................................................................13

3.2 SMBus Slave Interface

.......................................................................................................................................13

3.6 Hot remove

..................................................................................................................................13

3.7 Hot replace

..................................................................................................................................13

4.0 PIN CONFIGUREATION ..............................................................................................................14

5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16

5.1 2GB, 256Mx72 Module - M395T5663CZ4

........................................................................................16

5.2 4GB, 512Mx72 Module - M395T5160CZ4

.........................................................................................17

6.0 ELECTRICAL CHARACTERISTICS ............................................................................................18

7.0 CHANNEL INITIALIZATION ........................................................................................................24

3.5 Hot-add

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Rev. 1.52 April 2008

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