KESRX01G/IG/QP1S datasheet, PDF

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KESRX01G/IG/QP1S: DescriptionSPECIALTY TELECOM CIRCUIT, PDSO24, 0.150 INCH, MO-137AE, QSOP-24; CategoryWireless rf/communication Telecom circuit; File Size226KB，11 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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KESRX01G/IG/QP1S Overview

SPECIALTY TELECOM CIRCUIT, PDSO24, 0.150 INCH, MO-137AE, QSOP-24

KESRX01G/IG/QP1S Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	SSOP
package instruction	SSOP, SSOP24,.24
Contacts	24
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G24
length	8.65 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP24,.24
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	225
power supply	4.75/7 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum slew rate	0.003 mA
Nominal supply voltage	5 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.64 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm

KESRX01G/IG/QP1S Preview

KESRX01

290 - 460MHz ASK Receiver

Data Sheet

March 2006

The KESRX01 is a single chip ASK (Amplitude Shift Key)

Receiver IC. It is designed to operate in a variety of low power

radio applications including keyless entry, general domestic

and industrial remote control, RF tagging and local paging

systems.

This single conversion super–heterodyne receiver offers

an exceptionally high level of integration and performance.

The unique architecture enables data rates up to 50Kbits/sec

to be supported. All low power radio regulations, including

ETSI–ETS 300 220, and FCC, part 15, can easily be met.

Local oscillator generation is performed by an on–chip PLL

which uses an external crystal reference oscillator (4.5 to

7.2MHz). All popular radio frequencies (315MHz, 433.92MHz,

etc) can then be supported by simply choosing the appropriate

crystal frequency.

Particular emphasis has been placed on low current

consumption, with pulsed ON/OFF operation allowing <1mA

average current consumption to be achieved. The on–chip

VCO and IF significantly minimise the external components

needed thus reducing any re–radiation effects.

IFDC1

IFDC2

IF2

IF1

MIXIP

RFOP

VEERF

RFIN

DSN

DATAOP

PEAK

XTAL2

XTAL1

DF2

DF1

DF0

VCO2

VCO1

KESRX01

QP24

QPA24

Fig. 1 Pin connections - top view

FEATURES

Very low supply current (2.30mA typical)

Low external part count

–105dBm sensitivity (typical 315MHz)

Integrated VCO and IF Filters.

ORDERING INFORMATION

KESRX01G/IG/QP1T 24 Pin QSOP

KESRX01G/IG/QP1S 24 Pin QSOP

KESRX01G/IG/QP2Q 24 Pin QSOP*

KESRX01G/IG/QP2P 24 Pin QSOP*

*Pb Free Matte Tin

Tape& Reel

Tubes

Tape& Reel

Tubes

ABSOLUTE MAXIMUM RATINGS

All voltages relative to V

(0V)

Junction temperature, Tj

Storage temperature, Tstg

Supply voltage, V

max

Voltage on any pin, Vshort

–55 to +150°C

–0.5 to +8.0 V

–0.5 to +8.0V

DF2

DF1

DF0

IF DC1 IF DC2

IF 2

IF 1

MIXIP RFOP

PEAK DETECTOR

PEAK

DATA FILTER

DATA SLICER

–

DSN

VCC

VEE1

XTAL

OSCILLATOR

RSSI O/P

LOG

AMP

IF FILTER

600KHz

DATOP

MIXER

DIV 64

PHASE FREQUENCY

DETECTOR

VCO

RFIN

LNA

VEERF

XTAL 1 XTAL 2

VCO 1 VCO 2

Fig. 2. Block diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

1998-2006,

KESRX01

ELECTRICAL CHARACTERISTICS D.C.

amb

= -40 to + 85°C, V

= 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. They

apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.

Characteristic

Symbol

Min

Supply current

(PLL powered down)

Power down pin input logic high

Power down pin input logic low

Peak detector source current

Peak detector leakage

Data output Logic High

Data output Logic Low

Vil

0.7V

0.3V

-0.5

500

250

+0.5

µA

IIoad = 10µA

lload = 10µA

CC1

CC2

Value

Typ

2.30

1.90

Max

3.00

2.60

Units

Conditions

Vcc = 5V, all

= 5V, all

Electrostatic discharge (ESD) protection (human body model) 2KV minimum, all pins.

NOTES: Care must be taken not to power up the device with pins 7 and 8 shorted by a solder bridge, as operation with pin 7 grounded can damage

the device and result in low sensitivity.

ELECTRICAL CHARACTERISTICS A.C.

amb

= -40 to + 85°C, V

= 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. they

apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.

Characteristic

Sensitivity See Note 1

Signal handling See Note 2

LNA input impedance

Parallel combination R

Mixer input impedance

Parallel combination R

Crystal oscillator input

impedance

Integrated IF filter -3dB low

pass cut off frequency

Spurious reverse isolation to

RFIN See Note 3

Adjacent channel rejection

See Note 4

Notes:

1. Sensitivity is defined as the minimum average signal level measured at the input necessary to achieve a bit error ratio of

-2

where the input signal is a return to zero pulse (RZ) with an average duty cycle of 50%. The RF input is assumed to

be matched into 50Ω.

Measured in test circuit Fig. 6 with data filter bandwidth of 5KHz as shown and for a 2Kbit/s, 50% duty cycle signal.

2. Signal handling is defined as the maximum input signal capable of being succcessfully de-modulated. It is assumed the

input is ASK modulated with an extinction ratio of a least 40dB. The combination of this specification together with the

sensitivity specification gives a minimum signal handling range of 76dB. The RF input is assumed to be matched into 50Ω.

Measured in test circuit Fig. 6. with data filter bandwidth of 5KHz as shown.

3. -67dBm in 50Ω measured with the RF input matching network.

4. Adjacent channel rejection is defined for an interfering tone (ACR) dB above threshold and 10MHz offset from the carrier giving a 3dB

reduction in sensitivity i.e. the interfering tone is 4.74mV (rms) @ Fc

10MHz and to achieve the specified sensitivity the wanted signal

will have to be increased to 2.2µV (rms)

5. Please refer to Smith charts Fig.8 through to 10 covering frequency range 250-500MHz.

Symbol

Min

-23.5

2.65//2.2

1.15//1.1

-0.77

3dB

450

Value

Typ

-103

Units

Max

-100

dBm

3.61//2.2

1.21//1.62

KΩ//pF

KΩ

KHz

µV

(rms)

Conditions

= 50Ω, 434MHz, 2KB/s

= 5V; 25°C ambient; 434MHz

Also see note 5

= 5V; 25°C ambient; 434MHz

Also see note 5

C5 = C4 = 18pF

All

= 500Ω

10MHz offset from receiver VCO

-1.8

550

100

-2.1

750

ACR

KESRX01

PIN LISTING

Symbol

IFDC1

IFDC2

IF1

IF2

VCC

MIXIP

RFOP

VEERF

RFIN

DSN

DATAOP

PEAK

Description

IF amplifier – decouple point

IF amplifer – decouple point

Mixer output

IF amplifer input

Positive power supply

RF mixer input (tank)

RF amplifier output (tank)

RF amplifier ground

RF input (antenna)

Bit slicer comparator

negative input

Bit slicer comparator output

Peak detector output

Symbol

VEE

VCO1

VCO2

DF0

DF1

DF2

XTAL1

XTAL2

Description

Negative power supply (0V)

PLL power down

VCO maintaining amplifer

VCO maintaining amplifier

Not connected, unless to GND

Not connected,unless to GND

PLL loop filter O/P output

Data filter – external connection

Crystal oscillator

FUNCTION

Phase locked loop

The phase locked loop generates the local oscillator by

frequency multiplication of a crystal referenced oscillator.

Dividers

A divide by 64 prescaler is present in the PLL feedback

loop. The local oscillator frequency is then Fo=64xF

ref

. A

system operating at 433.92MHz (RFIN) with a 270KHz IF

frequency would require a reference of 6.77578MHz

(assuming mixer low side injection). Alternative choice of

crystal and tank components permit operation at specific

frequencies in the range 290 – 460MHz.

This phase detector has a triangle characteristic for an

input phase error in the range -2π <

θ<+2π

and has the benefit

of being a true frequency detector (as well as a phase

detector) and hence will always achieve lock for any initial

VCO frequency.

The charge pump provides an output current in the range

±30µA

and hence gives a phase detector gain of 4.8µA/rad.

The PLL loop characteristics such as lock-up time, capture

range, loop bandwidth and VCO reference sideband

suppression are controlled by the external loop filter.

For the intended application a 2nd order loop should be

sufficient as shown in the test circuit Fig. 6.

Phase detector

The phase detector used is a phase frequency detector

(PFD) with a current (charge pump) output.

VCO

A balanced configuration is used with the LC tank

connected externally across VCO1 and VCO2 Fig. 3.

DPb

VCO1

VCO2

Fig. 3 Input circuit of VCO and divider chain

KESRX01

External SAW resonator

For reduced power the PLL based oscillator can be

replaced by a SAW based oscillator. If pin PD is tied low (VEE)

the crystal oscillator, dividers and phase detector/charge

pump are powered down. The VCO can then be used as a

maintaining amplifier for an external SAW based oscillator.

The normal mode of operation is with PD set high (VCC) or

alternatively left unconnected. Note: the power down facility

is intended to be hard wired (either to VCC or VEE) and hence

the PD pin is not specified for operation with normal CMOS or

TTL logic levels.

/NC

MODE

PLL Enable

PLL Disable

Down converting mixer

The RF input is a.c. coupled into a doubly balanced mixer

configuration. Its input impedance is given in Fig.8.

IF filtering

The IF filter has a (nominal) bandpass response from

25KHz to 550KHz. The single high pass section is provided by

the combination of the external a.c. coupling capacitor

between IF1 and IF2 and an on chip resistor (nominal value

12kΩ). The low pass section is entirely on chip and to meet the

selectivity requirements (adjacent channel rejection) this filter

has 4 low pass poles with a Butterworth response.

IF amplifiers and demodulator

The majority of the receiver gain is provided in the form of

an IF limiting strip. These amplifiers are all d.c. coupled and

hence differential d.c. feedback is required. This is decoupled

externally at pins IFDC1 and IFDC2. The IF amplifier stages

also combine to provide a Received Signal Strength Indicator

(RSSI) function. Since the modulation is ASK and the RSSI

output has

a linear output for a logarithmic change on its input then the

RSSI output is the demodulated data. The only uncertainty is

the d.c. level.

Reference crystal oscillator

A crystal stabilised oscillator provides a reference clock for

the PLL. The oscillator is configured for parallel resonant

operation in the fundamental mode (typical operating

frequency of 4–7MHz). The crystal is connected between pins

XTAL1, XTAL2 with external components as shown in Fig. 6.

Note that this is a single transistor Colpitts oscillator where the

external load capacitors must be taken into account in

specifying the crystal. See Application Note AN207.

Data filter

Prior to the data slicer the demodulated data passes through

a low pass filter. This filter is a 2nd order Sallen–Key section

using an on chip voltage follower. External capacitors set the

cutoff frequency and filter Q. The value of the on chipresistors

is 100KΩ (nominal). See Fig. 4.

The cut-off frequency of the data filter,ƒo, should be set to

reduce high frequency noise into the data slicer without

distorting the wanted signal. Normally this would be at least

three times the data frequency.

RF amplifier

The RF amplifier consists of a low noise transistor in a

common emitter configuration. A separate emitter connection

is provided (VEERF) to reduce sensitivity to any common

impedance in this path. The amplifier is current source biased

so the signal (RFIN) should be a.c. coupled. The collector is

open circuit so that the gain can be set with an external tuned

load, Fig. 6. Its input impedance is given in Fig. 9 and output

impedance in Fig. 10.

DF0

100K

CUT OFF FREQUENCY = fo

DF1

DF2

o = 2 .

. fo . y

C1 = 2.Q

R .

C2 =

2 . Q . R

BESSEL

Q = 0.577

Y = 1.732

BUTTERWORTH

Q = 0.71

Y = 1.0

Fig. 4 Choosing data filter components

Example

To implement a Bessel response filter with a 10KHz 3dB cutoff

C1 = 106pF

C2 = 80pF

KESRX01

Bit slicer and Peak Detector

To provide maximum flexibility an independent data

comparator is provided. External circuitry must be provided to

obtain the bit slicer threshold level. Two basic approaches are

supported.

1. For coding schemes with no d.c. content (e.g. Manchester

coding or 33% / 66% pulse width encoding) this can be based

on the integrated d.c. level (using a series R and C). See

Application Note AN207.

2. For coding schemes with d.c. content (e.g. low duty cycle

pulse width modulation) an active peak detector is included.

The output at pin PEAK represents the peak level at the data

filter output (as shown in Fig.5). An external RC time constant

at this pin determines the maximum attack and decay times of

the peak detector. Typical values for the leakage and diode

current source capability are shown in the specifications. The

comparator has relatively low drive capability (push/pull

current source output of 20µA) and hence DATOP should not

be excessively loaded. On chip positive feedback around the

comparator provides a nominal hysteresis level of 20mV.

–

PEAK

–

INTERNAL CIRCUIT

PEAK LEVEL OUTPUT

Fig. 5 Peak detector output

Sensitivity

In digital radio systems, sensitivity is often defined as the

lowest signal level at the receiver input that will achieve a

specified Bit Error Ratio (BER) at the output. The sensitivity of

the KESRX01 receiver, when used in the 434MHz application

shown in Fig. 6, is typically –103dBm average power (ASK

modulated with 2kHz, 50% duty cycle square wave) to achieve

a 0.01 BER. The input was matched for a 50Ω signal source.

At 315MHz, –105dBm average power is typically achievable.

Consult the Applications Notes refered to at the end of this

Datasheet for detailed PCB design issues to secure

perfomance.

The local oscillator frequency is set at 433.65MHz with a

required accuracy of at least

100kHz (see section below) i.e

433.55MHz to 433.75MHz.

This guarantees that the IF (70KHz to 470KHz) falls within

the acceptance bandwidth of the IF filter.

The frequency of operation for such products in Europe is

433.05MHz to 434.79MHz. The choice of such a low IF

frequency ensures that any image falls within the regulatory

band. This in turn ensures that the receiver cannot be blocked

by the image response of an unwanted signal outside of this

band.

Choice of IF frequency and IF bandwidth

The IF frequency is selected to be nominally 270KHz with

the low frequency cut-off at 25KHz and the high frequency

cut-off at 550KHz (nominal). For worst case tolerances the

transmitter frequency may be 433.92MHz

100KHz. i.e from

433.82MHz to 434.02MHz (see transmitter design

specification application notes)

Frequency Accuracy

The stability of the local oscillator is equal to that of the

crystal reference oscillator. Therefore to obtain a final output

accuracy of

100KHz at 433MHz would require a crystal with

a tolerance specification of

230ppm. This tolerance should

encompass all causes e.g. initial accuracy, temperature

stability and ageing. Choose a tighter tolerance crystal for

increased frequency accuracy.

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Description	SPECIALTY TELECOM CIRCUIT, PDSO24, 0.150 INCH, MO-137AE, QSOP-24	SPECIALTY TELECOM CIRCUIT, PDSO24, 0.500 INCH, LEAD FREE, MO-137AE, QSOP-24	SPECIALTY TELECOM CIRCUIT, PDSO24, 0.150 INCH, MO-137AE, QSOP-24	SPECIALTY TELECOM CIRCUIT, PDSO24, 0.150 INCH, MO-137AE, QSOP-24	SPECIALTY TELECOM CIRCUIT, PDSO24, 0.500 INCH, LEAD FREE, MO-137AE, QSOP-24	Telecom Circuit, 1-Func, PDSO24, 0.150 INCH, MO-137AE, QSOP-24
Is it Rohs certified?	incompatible	conform to	conform to	conform to	conform to	incompatible
Maker	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi
Parts packaging code	SSOP	SSOP	SSOP	SSOP	SSOP	SSOP
package instruction	SSOP, SSOP24,.24	SSOP, SSOP24,.24	SSOP,	SSOP,	SSOP, SSOP24,.24	0.150 INCH, MO-137AE, QSOP-24
Contacts	24	24	24	24	24	24
Reach Compliance Code	unknown	unknown	unknown	compliant	unknown	unknown
JESD-30 code	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
length	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm
Number of functions	1	1	1	1	1	1
Number of terminals	24	24	24	24	24	24
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP	SSOP	SSOP	SSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.64 mm	0.64 mm	0.64 mm	0.64 mm	0.64 mm	0.64 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm
Encapsulate equivalent code	SSOP24,.24	SSOP24,.24	-	-	SSOP24,.24	SSOP24,.24
power supply	4.75/7 V	4.75/7 V	-	-	4.75/7 V	4.75/7 V
Maximum slew rate	0.003 mA	0.003 mA	-	-	0.003 mA	3 mA

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