PWR-82332
SMART POWER 3-PHASE MOTOR
DRIVE FOR SPACE APPLICATIONS
DESCRIPTION
The PWR-82332 is a Smart Power
3-phase Motor Drive hybrid. The
PWR-82332 uses a MOSFET out-
put stage with 400 VDC rating, and
can deliver 19A continuous current
to the load. Individual fast recovery
diodes are internally connected
across each of the six output tran-
sistors to clamp inductive flyback.
High and low-side input logic sig-
nals are XOR’d in each phase to
prevent simultaneous turn on of in-
line transistors, thus eliminating a
shoot thru condition. The internal
logic controls the high and low-side
gate drives for each phase and
operates from 5 V logic levels. The
internal power supply provides a
constant voltage source to the
floating high-side gate drives. This
provides constant output perfor-
mance for switching frequencies
from dc to 50 kHz.
APPLICATIONS
Packaged in a small case, this
hybrid is an excellent choice for high
performance, high-reliability motor
drives for servo-amps and speed
controls. Among the many applica-
tions are robotic arms; electro-
mechanical valve assemblies; actu-
ator systems; antenna and solar
panel positioning; fan and blower
motors for environmental condition-
ing; Reaction wheels; compressor
motors for cryogenic coolers. The
PWR-82332 hybrid is ideal for harsh
military/space environments where
shock, vibration, and temperature
extremes are evident. The PWR-
82332 operates over the -55°C to
+125°C temperature range and is
available with K-Level processing.
FEATURES
•
Small Size (3.0" x 2.3" x 0.40")
•
400 VDC Rating
•
19 A Continuous Current Capability
•
Class K Processing
•
SEU Immune for LET Level of 36
MeV/mg/cm2
•
Can Withstand 10 KRad (Si) Total
Dose Radiation
•
Space Station Qualified Drawing
#SSQ22691
•
High-Efficiency MOSFET Drive Stage
•
Direct Drive for Commutation Logic
•
6 Step Trapezoidal or Sinusoidal Drive
•
Four Quadrant Operation
Vb
VZ
VLPI
VUA
VLA
GND
POWER SUPPLY/BIAS GENERATION
VCC
A
VO
A
DRIVE
A
VSS
A
VUB
VLB
GND
DIGITAL
CONTROL
AND
PROTECTION
CIRCUITRY
VCC
B
VO
B
DRIVE
B
VSS
B
VUC
VLC
GND
VCC
C
VO
C
DRIVE
C
VSS
C
VSd
FIGURE 1. PWR-82332 BLOCK DIAGRAM
© 1993, 1999 Data Device Corporation
WARNING: ITAR CONTROLLED PRODUCT
The product(s) referenced on this data sheet or prod-
uct brief and certain related technical data is subject to
the U.S. Department of State International Traffic in
Arms Regulations (ITAR) 22 CFR 120-130 and may not
be exported without the appropriate prior authorization
from the Directorate of Defense Trade Controls, United
States Department of State. This datasheet includes
only basic marketing information on the function of the
product and therefore is not considered technical data
as defined in 22CFR 120.10.
TABLE 1. ABSOLUTE MAXIMUM RATINGS (SEE NOTE 1)
(TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
Supply Voltage (see note 2)
Bias Voltage
Logic Power-In Voltage
Input Logic Voltage
Output Current
Continuous
Pulsed (fo = 50kHz, duty cycle = 5%, Vcc = 120V
Operating Frequency
Case Operating Temperature
Storage Temperature Range
GND-Vss Differential Voltage
Dielectric Withstanding Voltage (all pins to package)
DMV
SYMBOL
Vcc
Vb
V
LPI
VU, VL, Vsd
I
O
I
OP
fo
Tc
Tcs
VALUE
400
50
5.5
6.0
19
25
50
-55 to +125
-65 to +150
±3V
500
UNITS
VDC
VDC
VDC
VDC
A
A
kHz
°C
°C
VDC or peak
VDC
TABLE 2. PWR-82332 SPECIFICATIONS
(TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
OUTPUT
Output Current Continuous
Supply Voltage
Output On-Resistance (each FET; see FIGURE 13)
Instant Forward Voltage (Flyback diode; see FIGURE 12)
Reverse Recovery Time (Flyback diode)
Reverse Leakage Current at Tc = +25°C
Reverse Leakage Current at Tc = +125°C
BIAS SUPPLY
Input Bias Supply (Tc = -55°C to +125°C)
Quiescent Bias Current (see note 2)
Bias Current (Tc = -55°C to +125°C;see FIGURES 9, 10, 11)
Inrush Current (Tc = -55°C to +125°C)
Logic Power Input Current
INPUT SIGNALS
High-Level Input Voltage
Low-Level Input Voltage
SWITCHING CHARACTERISTICS (see FIGURE 2)
Upper drive:
Turn-on Propagation Delay
Turn-off Propagation Delay
Shut-down Propagation Delay (see FIGURE 5)
Turn-on Rise Time
Turn-off Fall Time
Lower drive:
Turn-on Propagation Delay
Turn-off Propagation Delay
Shut-down Propagation Delay (see FIGURE 5)
Turn-on Rise Time
Turn-off Fall Time
MINIMUM PULSE WIDTH
THERMAL
Maximum Thermal Resistance
Maximum Lead Soldering Temperature
Junction Temperature Range
Case Operating Temperature
Case Storage Temperature
WEIGHT
NOTES:
1. Pulse width
≤
300µs, duty cycle
≤
2%.
2. VU, VL = Logic ‘0’ on pins 17, 18, 20, 21, 24 and 25.
3. Solder 1/8" from case for 5 seconds maximum.
SYMBOL
Io
Vcc
Ron
V
F
trr
I
R
I
R
Vb
Ibq
Ib
Iir
I
LPI
V
IH
V
IL
TEST CONDITIONS
MIN
TYP
MAX
19
400
0.25
1.6
50
280
7
50
40
100
1.4
7
3.15
0.9
UNITS
A
V
Ohm
V
nsec
µA
mA
V
mA
mA
A
mA
V
V
120
I
F
= 15A (see note 1)
I
F
= 15A (see note 1)
I
F
= 1A, I
R
= 1A
Vcc = 400V V
U
= V
L
= Logic 0
,
Vcc = 400V V
U
= V
L
= Logic 0
,
14
Vb = 28V
Vb = 28V, fo = 30kHz
Vb = 28V
V
LPI
= 5.0V
td (on)
td (off)
tsd
tr
tf
td (on)
td (off)
tsd
tr
tf
tpw
θ
j-c
Ts
Tj
Tco
Tcs
Io = 15A Peak
Vcc = 120V
690
1375
800
300
300
675
1050
700
300
300
175
0.85
250
150
125
150
6.125 (175)
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
°C/W
°C
°C
°C
°C
oz (g)
see note 3
each transistor
-55
-55
-55
2
INTRODUCTION
The 3-Phase PWR-82332 is a 19A motor drive rated at 400V.
The PWR-82332 uses a MOSFET output stage for high speed,
high current, and high-efficiency operation. This motor drive is
ideal for use in high-performance motion control systems, servo
amplifiers, and motor speed control designs. Furthermore, multi-
axis systems requiring multiple drive stages can-benefit from the
small size of this power drive.
The PWR-82332 can be driven directly from commutation logic,
DSP, or a custom ASIC that supplies digital signals to control the
upper and lower transistors of each phase. This highly integrated
drive stage has digital inputs that control the high and low side of
each phase. Digital protection of each phase eliminates an in-line
firing condition, by preventing simultaneous turn-on of both the
upper and lower transistors in a given phase. The PWR-82332 has
a ground referenced low-side gate drive. An internal dc-dc con-
verter supplies a floating output to each of the 3 high side drives.
This provides a continuous high-side gate drive even during a
motor stall. The high and low-side gate drivers control the N-
channel MOSFET output stage. The MOSFETs used in the
PWR-82332 allow output switching up to 50 kHz. A flyback
diode parallels each output transistor and controls the regenera-
tive energy produced by the motor. These fast recovery diodes
have faster reverse switching times than the intrinsic body diode
of the MOSFETS used in the PWR-82332. Care should be taken
to adequately heatsink these motor drives to maintain a case
temperature under 125°C. Junction temperatures should not
exceed 150°C. The PWR-82332 does not have an internal
short-circuit or overcurrent protection. For protection of the out-
put transistors, these features must be added external to the
hybrid.
INPUTS:
(VUA, VUB, VUC)
INPUTS:
(VLA, VLB, VLC)
50%
OUTPUTS:
(VOA, VOB, VOC)
t
r
t
f
50%
OUTPUTS:
(VOA, VOB, VOC)
t
r
t
f
90%
50%
10%
90%
50%
10%
t
d
(ON)
t
d
(OFF)
t
d
(ON)
t
d
(OFF)
FIGURE 2. INPUT/OUTPUT TIMING RELATIONSHIPS
+5V
OPEN
+15V
≤
V
≤
+50Vdc
+120Vdc
BIAS VOLTAGES
The PWR-82332 motor drive hybrid requires a single input bias
supply for operation. The hybrid generates three independent,
floating supplies internally, which eliminates the need for exter-
nal bias voltages for each phase.
In order for the internal power supply to generate these voltages,
the input bias voltages (V
b
) must be from 15 to 50 Vdc.
Any voltage available in the system in the 15 to 50 Vdc range can
be directly connected to the V
b
pin of the hybrid. (See FIGURE
3).
A 0.01
μF
decoupling capacitor must be connected between V
b
(pin 12) and GND and VLPI (pin 16) to GND.
0.01µF
0.01µF
16
V
LPI
13
V
Z
12
V
B
3
7 11
V
CC
PWR-82332
FIGURE 3. CONNECTION TO BUS VOLTAGE,
INPUT BIAS VOLTAGE AND LOGIC
POWER INPUT VOLTAGE
3
DIGITALLY CONTROLLED INPUTS
The PWR-82332 digital inputs can be driven with any type of 5
V logic, such as TTL or CMOS logic. PIN 16 is the logic power
input (VLPI) for the digital circuitry inside the hybrid. An external
5 V power supply must be connected between this pin and GND.
A 0.01
μ
F ceramic capacitor must be placed between this pin
and GND as close to the hybrid as possible see (FIGURE 3).
The commutation/control circuitry can be as simple as discrete
logic with PWM, or as sophisticated as a microprocessor or cus-
tom ASIC, depending on the system requirements. The Block
diagram in FIGURE 4 shows a typical interface of the PWR-
82332 with a motor and commutation logic in a Servo-Amp
System.
not respond to signals on the V
L
or V
U
inputs while the Vsd has
a logic ‘1’ applied. See FIGURE 5. When the user or the sense
circuitry ( as in FIGURE 6) returns the Vsd input to a logic ‘0’, the
output transistors will respond to the corresponding digital input.
This feature can be used with the external current limit or tem-
perature sense circuitry to disable the drive if a fault condition
occurs (see FIGURE 6).
INTERNAL PROTECTION CIRCUITRY
The hybrid contains digital protection circuitry, which prevents in-
line transistors from conducting simultaneously. This, in effect,
would short circuit the power supply and would damage the out-
put stage of the hybrid. The circuitry allows only proper input sig-
nal patterns to cause output conduction. TABLE 3. shows these
timing relationships. If an improper input requested that the
upper and lower transistors of the same phase conduct together,
the output would be a high impedance until removal of the illegal
code from the input of the PWR-82332. A dead time is not
required for the signals at the V
U
and V
L
pins.
SHUT-DOWN INPUT (Vsd)
Pin 23 (Vsd) provides a digital shut-down input, which allows the
user to completely turn off both the upper and lower output tran-
sistors in all 3 phases. Application of a logic ‘1’ to the Vsd input
will disable the Digital/Control Protection circuitry thereby turning
off all output transistors. The circuitry remains disabled and will
POWER SUPPLY/BIAS GENERATION
CC A
V
CC
OA
SS A
+
CC B
Ω
HALL
EFFECT
DEVICE
OB
MOTOR
SS B
CC C
OC
SS C
CRITICAL GROUND PATH
To prevent damage to the internal drive circuitry, the differential voltage between
GND (pins 19,22,26) and Vss (pins 1, 5, 8) must not exceed ± 3V max, dc or peak
FIGURE 4. PWR-82332 TYPICAL INTERFACE WITH A MOTOR
4
1
V
UA
V
UB
V
UC
V
LA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
0
1
0
1
0
1
0
1
0
1
0
1
0
H
Z
L
H
Z
L
H
Z
L
V
LB
V
LC
V
Sd
1
0
t
en
t
sd
V
Sd
V
OA
H
V
OA
Z
L
V
OB
V
OC
FIGURE 5. SHUT-DOWN (Vsd) TIMING RELATIONSHIP
5V
15V
120V
INPUT
COMMANDS
COMMUTATION
LOGIC
18
17
21
20
25
24
23
16
12
11
7
3
9
6
PWR82332
MOTOR
2
CURRENT
SENSE
CIRCUITRY
VSd
1
Vss
5
19,22,26
8
R SENSE
FIGURE 6. FUNCTIONAL SHUT-DOWN INPUT USED WITH CURRENT-SENSING CIRCUITRY
5
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