Parity Generator/Checker, FCT Series, 9-Bit, Complementary Output, CMOS, PZIP20,
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Quality Semiconductor Inc |
| package instruction | ZIP, ZIP20,.1 |
| Reach Compliance Code | unknown |
| Other features | ODD/EVEN PARITY GENERATOR; OPTIONAL REGISTERED COMPLEMENTARY OUTPUTS |
| series | FCT |
| JESD-30 code | R-PZIP-T20 |
| JESD-609 code | e0 |
| Load capacitance (CL) | 50 pF |
| Logic integrated circuit type | PARITY GENERATOR/CHECKER |
| Number of digits | 9 |
| Number of functions | 1 |
| Number of terminals | 20 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output polarity | COMPLEMENTARY |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | ZIP |
| Encapsulate equivalent code | ZIP20,.1 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| propagation delay (tpd) | 10 ns |
| Certification status | Not Qualified |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 1.27 mm |
| Terminal location | ZIG-ZAG |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
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