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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 840022AGLFT
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840022AGLFT

Description
Clock Generator, 125MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size264KB，12 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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840022AGLFT Overview

Clock Generator, 125MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8

840022AGLFT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP8,.25
Contacts8
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G8
JESD-609 codee3
length4.4 mm
Humidity sensitivity level1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency125 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency25 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER

840022AGLFT Preview

PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
ICS840022
G
ENERAL
D
ESCRIPTION
The ICS840022 is a Gigabit Ether net Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from IDT.
The ICS840022 uses a 25MHz crystal to syn-
thesize 125MHz or 62.5MHz. The ICS840022 has
excellent phase jitter performance, over the 1.875MHz – 20MHz
integration range. The ICS840022 is packaged in a small 8-pin
TSSOP, making it ideal for use in systems with limited board
space.
F
EATURES
•
One LVCMOS/LVTTL output, 7Ω output impedence
•
Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
•
Output frequencies: 125MHz or 62.5MHz (selectable)
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.55ps (typical)
•
RMS phase noise at 125MHz:
Offset
Noise Power
100Hz ............. -106.3 dBc/Hz
1kHz ............. -126.3 dBc/Hz
10kHz ............. -131.7 dBc/Hz
100kHz ............. -130.8 dBc/Hz
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
•
Industrial temperature information available upon request
IC
S
F
UNCTION
T
ABLE
Inputs
FREQ_SEL
0
1
Output Frequencies
(with a 25MHz crystal)
125MHz
62.5MHz
B
LOCK
D
IAGRAM
OE
FREQ_SEL
P
IN
A
SSIGNMENT
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
GND
FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
560MHz-680MHz
w/25MHz Ref.
÷5
0
Q
ICS840022
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
÷10
1
M = ÷25 (fixed)
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
1
ICS840022AG REV. A JANUARY 26, 2007
ICS840022
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
FREQ_SEL
GND
Q
V
DD
Power
Input
Input
Input
Power
Output
Power
Type
Description
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled.
Pullup
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω output impedence.
Core supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDA
= 3.465V
Test Conditions
Minimum
Typical
4
TBD
51
51
7
Maximum
Units
pF
pF
kΩ
kΩ
Ω
T
ABLE
3. C
ONROL
F
UNCTION
T
ABLE
Control Inputs
OE
0
1
Output
Q
Hi-Z
Active
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
2
ICS840022AG REV. A JANUARY 26, 2007
ICS840022
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
101.7°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
45
8
Maximum
3.465
3.465
Units
V
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
FREQ_SEL
OE
FREQ_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MH z
Ω
pF
Maximum
Units
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
125MHz, (Intergration Range:
1.875MHz - 20MHz)
62.5MHz, (Intergration Range:
1.875MHz - 20MHz)
20% to 80%
Test Conditions
Minimum
Typical
125
62.5
0.55
0.50
35 0
50
Maximum
Units
MHz
MHz
ps
ps
ps
%
t
jit(Ø)
t
R
/ t
F
RMS Phase Jitter; NOTE 1
Output Rise/Fall Time
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plot.
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
3
ICS840022AG REV. A JANUARY 26, 2007
ICS840022
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PRELIMINARY
T
YPICAL
P
HASE
N
OISE AT
62.5MH
Z
(3.3V)
-10
-20
-30
-40
-50
➤
Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps
0
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
Raw Phase Noise Data
➤
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
(3.3V)
0
-20
-30
-40
-50
➤
Phase Noise Result by adding
Gb Ethernet Filter to raw data
1M
10M
100M
100k
O
FFSET
F
REQUENCY
(H
Z
)
➤
Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.50ps
-10
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
Raw Phase Noise Data
➤
-120
-130
-140
-150
-170
-180
-190
100
1k
➤
Phase Noise Result by adding
Gb Ethernet Filter to raw data
10k
100k
1M
10M
100M
-160
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
4
ICS840022AG REV. A JANUARY 26, 2007
ICS840022
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V ± 5%
Phase Noise Plot
Noise Power
V
DD,
V
DDA
Qx
SCOPE
Phase Noise Mask
LVCMOS
GND
f
1
Offset Frequency
f
2
-1.65V ± 5%
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
80%
Q
80%
20%
t
PW
t
PERIOD
Clock
Outputs
20%
t
R
t
F
odc =
t
PW
t
PERIOD
x 100%
LVCMOS O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
LVCMOS O
UTPUT
R
ISE
/F
ALL
T
IME
IDT
™
/ ICS
™
LVCMOS/LVTTL CLOCK GENERATOR
5
ICS840022AG REV. A JANUARY 26, 2007
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

840022AGLFT Related Products

840022AGLFT 840022AGLF
Description Clock Generator, 125MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8 Clock Generator, 125MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction TSSOP, TSSOP8,.25 TSSOP, TSSOP8,.25
Contacts 8 8
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G8 R-PDSO-G8
JESD-609 code e3 e3
length 4.4 mm 4.4 mm
Humidity sensitivity level 1 1
Number of terminals 8 8
Maximum operating temperature 70 °C 70 °C
Maximum output clock frequency 125 MHz 125 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP8,.25 TSSOP8,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Master clock/crystal nominal frequency 25 MHz 25 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 3 mm 3 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER

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