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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 844011AGT
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844011AGT

Description
Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size744KB，12 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

844011AGT Overview

Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8

844011AGT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP8,.25
Contacts8
Reach Compliance Codenot_compliant
ECCN codeEAR99
Other featuresALSO OPERATES AT 3.3V SUPPLY
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.4 mm
Humidity sensitivity level1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency113.33 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)240
power supply2.5/3.3 V
Master clock/crystal nominal frequency28.3 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width3 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER

844011AGT Preview

FemtoClock
™
Crystal-to-LVDS
Clock Generator
General Description
The ICS844011 is a Fibre Channel Clock Generator
and a member of the HiPerClocks
TM
family of high
HiPerClockS™
performance devices from IDT. The ICS844011 uses
an 18pF parallel resonant crystal over the range of
20.4MHz - 28.3MHz. For Fibre Channel applications, a
26.5625MHz crystal is used. The ICS844011 has excellent <1ps
phase jitter performance, over the 637kHz - 10MHz integration
range. The ICS844011 is packaged in a small 8-pin TSSOP, making
it ideal for use in systems with limited board space.
ICS844011
PRELIMINARY DATA SHEET
Features
•
•
•
•
•
•
•
•
•
One differential LVDS clock output pair
Crystal interface designed for 18pF parallel resonant crystals
(20.4MHz – 28.3MHz)
Output frequency range: 81.66MHz – 113.33MHz
VCO range: 490MHz – 680MHz
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.75ps (typical)
RMS phase jitter @ 156.25MHz, (1.875MHz - 20MHz):
0.45ps (typical)
Full 3.3V or 2.5V operating supply
Available in both standard (RoHs 5) and lead-free (RoHS 6)
packages
0°C to 70°C ambient operating temperature
ICS
Common Configuration Table – Fibre Channel
Inputs
Crystal Frequency (MHz)
26.5625
25
M
24
24
N
6
6
Multiplication Value M/N
4
4
Output Frequency (MHz)
106.25
100
Block Diagram
OE
Pullup
Pin Assignment
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷6
(fixed)
Q
nQ
M = ÷24
(fixed)
ICS844011
8-lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
ICS844011AG REV. B AUGUST 28, 2009
1
©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet
FEMTOCLOCK
™
CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT,
XTAL_IN
OE
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog power supply.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ
output is in a high impedance state. LVCMOS/LVTTL interface levels.
Differential clock output. LVDS interface levels.
Core supply pin.
NOTE:
Pullup
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
ICS844011AG REV. B AUGUST 28, 2009
2
©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet
FEMTOCLOCK
™
CRYSTAL-TO-LVDS CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
129.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.07
Typical
3.3
3.3
90
7
Maximum
3.465
V
DD
Units
V
V
mA
mA
Table 3B. Power Supply DC Characteristics, V
DD
= 2.5V±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.07
Typical
2.5
2.5
85
7
Maximum
2.625
V
DD
Units
V
V
mA
mA
Table 3C. LVCMOS/LVTTL Input DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
OE
OE
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
ICS844011AG REV. B AUGUST 28, 2009
3
©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet
FEMTOCLOCK
™
CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 3D. LVDS DC Characteristics,
V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
50
1.25
50
Maximum
Units
mV
mV
V
mV
Table 3E. LVDS DC Characteristics,
V
DD
= 2.5V±5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
50
1.2
50
Maximum
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
20.4
Test Conditions
Minimum
Typical
Fundamental
28.3
50
7
1
MHz
Ω
pF
mW
Maximum
Units
ICS844011AG REV. B AUGUST 28, 2009
4
©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet
FEMTOCLOCK
™
CRYSTAL-TO-LVDS CLOCK GENERATOR
AC Characteristics
Table 5A. AC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
106.25MHz, Integration Range:
637kHz – 10MHz
100MHz, Integration Range:
637kHz – 10MHz
20% to 80%
0.75
275
50
Test Conditions
Minimum
81.66
Typical
Maximum
113.33
Units
MHz
ps
ps
ps
%
tjit(Ø)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to the phase noise plot.
Table 5B. AC Characteristics, V
DD
= 2.5V±5%, T
A
= 0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
106.25MHz, Integration Range:
637kHz – 10MHz
100MHz, Integration Range:
637kHz – 10MHz
20% to 80%
Test Conditions
Minimum
81.66
0.45
0.93
295
50
Typical
Maximum
113.33
Units
MHz
ps
ps
ps
%
tjit(Ø)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to the phase noise plot.
ICS844011AG REV. B AUGUST 28, 2009
5
©2009 Integrated Device Technology, Inc.
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

844011AGT Related Products

844011AGT 844011AG
Description Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8 Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction TSSOP, TSSOP8,.25 TSSOP, TSSOP8,.25
Contacts 8 8
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
Other features ALSO OPERATES AT 3.3V SUPPLY ALSO OPERATES AT 3.3V SUPPLY
JESD-30 code R-PDSO-G8 R-PDSO-G8
JESD-609 code e0 e0
length 4.4 mm 4.4 mm
Humidity sensitivity level 1 1
Number of terminals 8 8
Maximum operating temperature 70 °C 70 °C
Maximum output clock frequency 113.33 MHz 113.33 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP8,.25 TSSOP8,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 240 240
power supply 2.5/3.3 V 2.5/3.3 V
Master clock/crystal nominal frequency 28.3 MHz 28.3 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage 2.625 V 2.625 V
Minimum supply voltage 2.375 V 2.375 V
Nominal supply voltage 2.5 V 2.5 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 20 20
width 3 mm 3 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER

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