FEMTOCLOCKS™ CRYSTAL-TO-HSTL
FREQUENCY SYNTHESIZER
ICS8421002I
G
ENERAL
D
ESCRIPTION
The ICS8421002I is a 2 output HSTL Synthesizer
optimized to generate Fibre Channel reference clock
HiPerClockS™
frequencies and is a member of the HiPerClocks
TM
family of high performance clock solutions from IDT.
Using a 26.5625MHz 18pF parallel resonant crystal,
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 106.25MHz and 53.125MHz. The ICS8421002I uses
IDT’s 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting Fibre
Channel jitter requirements. The ICS8421002I is packaged in a
small 20-pin TSSOP package.
F
EATURES
• Two HSTL outputs (VOHmax = 1.5V)
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) an lead-free (RoHS 6)
packages
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
23.4375
Inputs
M Divider N Divider
Value
Value
24
3
24
24
24
24
4
6
12
3
M/N
Divider Value
8
6
4
2
8
Output
Frequency
(MHz)
212.5
159.375
106.25
53.125
187.5
P
IN
A
SSIGNMENT
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
nQ1
GND
V
DD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
F_SEL1 F_SEL0
0
0
1
1
0
0
1
0
1
0
ICS8421002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Q0
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
REF_CLK
Pulldown
26.5625MHz
2
1
F_SEL[1:0]
0 0 ÷3
(default)
1
01
10
11
÷4
÷6
÷12
nQ0
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
Q1
nQ1
0
M = 24 (fixed)
MR
Pulldown
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
1
ICS8421002I REV B
MARCH 02,
2009
ICS8421002I
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 20
3, 4
5
Name
nc
V
DDO
Q0, nQ0
MR
Type
Unused
Power
Ouput
Input
Description
No connect.
Output supply pins.
Differential output pair. HSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. HSTL interface levels.
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
nPLL_SEL
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
REF_CLK
nXTAL_SEL
GND
nQ1, Q1
Input
Power
Input
Power
Input
Input
Input
Power
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
2
ICS8421002I REV B MARCH 02, 2009
ICS8421002I
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
73.2°C/W (0 lfpm)
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
3.3
1.8
Maximum
3.465
3.465
2.0
110
12
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
Maximum
2.625
2.625
2.0
96
12
Units
V
V
V
mA
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 1.8V±0.2V,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V
or 2.5V
V
DD
= 3.465V or 2.5V,
V
IN
= 0V
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
-150
µA
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
3
ICS8421002I REV B MARCH 02, 2009
ICS8421002I
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
T
ABLE
3D. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
OX
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
1.0
0
40
0.6
Typical
Maximum
1.5
0.5
60
1. 3
Units
V
V
%
V
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
3E. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
OX
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
0.8
0
40
0.5
Typical
Maximum
1.5
0.6
60
1. 5
Units
V
V
%
V
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
26.5625
Maximum
28.33
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
4
ICS8421002I REV B MARCH 02, 2009
ICS8421002I
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum
186.67
140
93.33
46.67
0.59
0.51
0.56
0.69
0.66
175
875
52
56
Typical
Maximum
226.66
170
113.33
56.66
20
212.5MHz, (637kHz - 10MHz)
187.5MHz, (1.875MHz - 20MHz)
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
t
sk(o)
Output Skew; NOTE 1, 3
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
159.375MHz, (637kHz - 10MHz)
106.25MHz, (637kHz - 10MHz)
53.125MHz, (637kHz - 10MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N Divider = 4, 6, 12
48
N Divider = 3
44
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum
186.67
140
93.33
46.67
0.60
0.70
0.64
0.70
0.68
200
700
52
56
Typical
Maximum
226.66
170
113.33
56.66
20
212.5MHz, (637kHz - 10MHz)
187.5MHz, (1.875MHz - 20MHz)
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
t
sk(o)
Output Skew; NOTE 1, 3
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
159.375MHz, (637kHz - 10MHz)
106.25MHz, (637kHz - 10MHz)
53.125MHz, (637kHz - 10MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N Divider = 4, 6, 12
48
N Divider = 3
44
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
5
ICS8421002I REV B MARCH 02, 2009
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