ISPLSI1048E-50LQN datasheet, PDF

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ISPLSI1048E-50LQN: DescriptionEE PLD, 24.5ns, 192-Cell, CMOS, PQFP128, LEAD FREE, PLASTIC, QFP-128; CategoryProgrammable logic devices Programmable logic; File Size276KB，17 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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ISPLSI1048E-50LQN Overview

EE PLD, 24.5ns, 192-Cell, CMOS, PQFP128, LEAD FREE, PLASTIC, QFP-128

ISPLSI1048E-50LQN Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	QFP
package instruction	QFP, QFP128,1.2SQ,32
Contacts	128
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	YES
maximum clock frequency	42 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G128
JESD-609 code	e3
JTAG BST	NO
length	28 mm
Humidity sensitivity level	3
Dedicated input times	8
Number of I/O lines	96
Number of macro cells	192
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 96 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP128,1.2SQ,32
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Programmable logic type	EE PLD
propagation delay	24.5 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	28 mm

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Lead-

Free

Package

Options

Available!

ispLSI 1048E

In-System Programmable High Density PLD

Functional Block Diagram

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

Output Routing Pool

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

— 96 I/O Pins, Twelve Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally and Pin-out Compatible to ispLSI 1048C

TECHNOLOGY

• HIGH PERFORMANCE

—

max

= 125 MHz Maximum Operating Frequency

—

= 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

CMOS

Output Routing Pool

E7 E6 E5 E4 E3 E2 E1 E0

Logic

D Q

Global Routing Pool (GRP)

Array

GLB

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

CLK

0139G1A-isp

Description

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Reprogram Soldered Devices for Faster Prototyping

The ispLSI 1048E is a High Density Programmable Logic

Device containing 288 Registers, 96 Universal I/O pins,

12 Dedicated Input pins, four Dedicated Clock Input pins,

two dedicated Global OE input pins, and a Global Routing

Pool (GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1048E offers

5V non-volatile in-system programmability of the logic, as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1048 archi-

tecture, the ispLSI 1048E device adds two new global

output enable pins and two additional dedicated inputs.

The basic unit of logic on the ispLSI 1048E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 1048E device. Each GLB has 18 inputs, a pro-

grammable AND/OR/Exclusive OR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

— Flexible Pin Placement

to change without notice.

— Lead-Free Package Options

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Synchronous and Asynchronous Clocks

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

1048e_12

Output Routing Pool

D Q

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