700MHZ, Low Jitter, Crystal-To-3.3V
LVPECL Frequency Synthesizer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES ON (JULY 26, 2014)
ICS84329B-01
DATASHEET
General Description
The ICS84329B-01 is a general purpose, single output high
frequency synthesizer. The VCO operates at a frequency range of
250MHz to 700MHz. The VCO frequency is programmed in steps
equal to the value of the crystal frequency divided by 16. The VCO
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The output can be
configured to divide the VCO frequency by 1, 2, 4, and 8. Output
frequency steps as small as 125kHz to 1MHz can be achieved
using a 16MHz crystal depending on the output dividers.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL, no external loop filter requirements
One differential 3.3V LVPECL output pair
Crystal oscillator interface
Output frequency range: 31.25MHz – 700MHz
VCO range: 250MHz – 700MHz
Parallel interface for programming counter and output dividers
during power-up
Serial 3 wire interface
RMS period jitter: 5.5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Use replacement part: 8T49N203A-dddNLGI
Pin Assignments
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
V
EE
TEST
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL_OUT
XTAL_IN
nc
nc
V
CCA
S_LOAD
S_DATA
S_CLOCK
V
CC
FOUT
nFOUT
V
EE
nFOUT
FOUT
ICS84329B-01
28 Lead SOIC
7.5mm x 18.05mm x 2.25mm
package body
M Package
Top View
Block Diagram
TEST
V
CC
V
EE
V
CC
25 24 23 22 21 20 19
XTAL_OUT
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
nc
XTAL_IN
26
27
28
1
2
3
4
5
XTAL_OUT
V
EE
XTAL_IN
OSC
18
17
16
15
14
13
12
N1
N0
M8
M7
M6
M5
M4
÷M
PHASE DETECTOR
1
VCO
0
÷16
PLL
÷1
÷2
÷4
÷8
6
V
CC
7
nP_LOAD
8
M0
9
M1
10 11
M2
M3
FOUT
nFOUT
ICS84329B-01
28 Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
V Package
Top View
S_LOAD
S_DATA
DA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
Pullup
CONFIGURATION
INTERFACE
LOGIC
TEST
M0:M8
N0:N1
Pullup
Pullup
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
1
ICS84329BM-01 REV. C AUGUST 19, 2013
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The ICS84329B-01 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior
to the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range
of 250MHz to 700MHz. The output of the M divider is also applied
to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS84329B-01 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel mode the
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
nP_LOAD input is LOW. The data on inputs M0 through M8 and N0
through N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fVCO = fXTAL x M
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock are defined as
250
M
511.
The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are
latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is
held HIGH, data at the S_DATA input is passed directly to the M
divider on each rising edge of S_CLOCK. The serial mode can be
used to program the M and N bits and test bits T2:T0. The internal
resistors T2:T0 determine the state of the TEST output as follows:
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK ÷ N Divider
fOUT
TEST Output
Shift Register Out
HIGH
PLL Reference XTAL ÷16
(VCO ÷ M) /2 (non 50% Duty Cycle M Divider)
fOUT, LVCMOS Output Frequency < 200MHz
LOW
S_CLOCK ÷ M (non 50% Duty Cycle M Divider)
fOUT ÷ 4
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T2
S
T1
H
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
nP_LOAD
Time
Figure 1. Parallel & Serial Load Operations
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
2
ICS84329BM-01 REV. C AUGUST 19, 2013
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Name
M0, M1, M2, M3, M4,
M5, M6, M7, M8
N0, N1
V
EE
TEST
V
CC
FOUT, nFOUT
nc
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_IN
XTAL_OUT
nP_LOAD
Input
Input
Power
Output
Power
Output
Unused
Input
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Type
Pullup
Pullup
Description
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
Determines N output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
Core supply pins.
Differential output pair for the synthesizer. LVPECL interface levels.
No connect.
Clocks the serial data present at S_DATA input into the shift register on the rising
edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider,
and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL
interface levels.
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
3
ICS84329BM-01 REV. C AUGUST, 19, 2013
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD
X
L
H
H
H
H
M
X
Data
Data
X
X
X
X
N
X
Data
Data
X
X
X
X
S_LOAD
X
X
L
L
L
S_CLOCK
X
X
X
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on S_DATA
on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
NOTE:L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
250
251
252
253
•
•
509
510
511
256
M Divide
250
251
252
253
•
•
509
510
511
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
8
M3
1
1
1
1
•
•
1
1
1
4
M2
0
0
1
1
•
•
1
1
1
2
M1
1
1
0
0
•
•
0
1
1
1
M0
0
1
0
1
•
•
1
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
250
125
62.5
31.25
Maximum
700
350
175
87.5
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
4
ICS84329BM-01 REV. C AUGUST 19, 2013
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
28 Lead SOIC
28 Lead PLCC
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2C/W (0 lfpm)
37.8C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
I
CC
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
125
15
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
S_CLOCK,
S_DATA, S_LOAD
nP_LOAD,
M0:M8, N0, N1
S_CLOCK,
S_DATA, S_LOAD
nP_LOAD,
M0:M8, N0, N1
TEST; NOTE 1
TEST; NOTE 1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.3V±5%
V
CC
= 3.3V±5%
-5
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
I
IL
V
OH
V
OL
Input
Low Current
Output High Voltage
Output
Low Voltage
NOTE 1: Outputs terminated with 50
to V
CC
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
5
ICS84329BM-01 REV. C AUGUST, 19, 2013
京公网安备 11010802033920号
EEWORLD
