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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ICS843204AGI-01T
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ICS843204AGI-01T

Description
Clock Generator, 156.25MHz, PDSO48, 6.10 X 12.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-48
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size258KB，13 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

ICS843204AGI-01T Overview

Clock Generator, 156.25MHz, PDSO48, 6.10 X 12.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-48

ICS843204AGI-01T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts48
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G48
JESD-609 codee0
length12.5 mm
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency156.25 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
Master clock/crystal nominal frequency25 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER

ICS843204AGI-01T Preview

FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843204I-01
G
ENERAL
D
ESCRIPTION
The ICS843204I-01 is a 4 output LVPECL Synthe-
sizer optimized to generate Gigabit Ethernet and
HiPerClockS™
SONET reference clock frequencies and is a
member of the HiPerClocks
TM
family of high
performance clock solutions from IDT. Using a
19.44MHz and 25MHz, 18pF parallel resonant cr ystal,
155.52MHz and 156.25MHz frequencies can be generated.
The ICS843204I-01 uses IDT’s FemtoClock
TM
low phase noise
VCO technology and can achieve 1ps or lower typical RMS
phase jitter.
F
EATURES
• Four 3.3V LVPECL outputs
• Selectable crystal oscillator interface or clock inputs
• Supports the following output frequencies: 155.52MHz
and 156.25MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz - 13MHz): 0.6ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.7ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
nPLL_BYPASS_A
Pullup
IN_SELA
Pullup
CLK0
Pulldown
25MHz
P
IN
A
SSIGNMENT
nQA1
QA1
nQA0
QA0
nc
V
CCO
_
A
SELA1
SELA0
nPLL_BYPASS_A
nc
nc
nc
nc
XTAL_IN1
XTAL_OUT1
CLK1
nCLK1
IN_SELB
V
CCO
_
B
nc
QB0
nQB0
QB1
nQB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IN_SELA
CLK0
XTAL_IN0
XTAL_OUT0
nc
V
EE
OEA0
OEA1
V
CC
V
CCA
nPLL_BYPASS_B
nc
SELB0
V
EE
OEB0
OEB1
V
CC
SELB1
V
CCA
nc
nc
nc
nc
nc
SELA0
OEA0
QA0
XTAL_IN0
OSC
XTAL_OUT0
PLL
÷4
156.25MHz
0
1
SELA1
OEA1
QA1
nQA1
nQA0
625MHz
nPLL_BYPASS_B
Pullup
IN_SELB
Pullup
CLK1
Pulldown
0
1
nCLK1
Pullup/pulldown
19.44MHz
SELB0
OEB0
QB0
nQB0
XTAL_IN1
0
OSC
XTAL_OUT1
PLL
622.08MHz
÷4
155.52MHz
1
SELB0
OEB1
ICS843204I-01
QB1
nQB1
0
1
48 Lead TSSOP
6.1mm x 12.5mm x 0.925mm
package body
G Package
Top View
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 10, 11, 12,
13, 20, 25, 26,
27, 28, 29, 37,
44
6
7
8
9
14,
15
16
17
18
19
21, 22
23, 24
30, 39
Name
nQA1, QA1
nQA0, QA0
nc
V
CCO_A
SELA1
SELA0
nPLL_BYPASS_A
XTAL_IN1,
XTAL_OUT1
CLK1
nCLK1
IN_SELB
V
CCO_B
QB0, nQB0
QB1, nQB1
V
CCA
Type
Output
Output
Unused
Power
Input
Input
Input
Input
Input
Input
Input
Power
Ouput
Ouput
Power
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
No connect.
Output supply pin for Bank A outputs.
Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. When LOW,
Pulldown
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. When LOW,
Pulldown
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Pullup
When LOW, PLL is bypassed. When HIGH, PLL output is active.
Parallel resonant cr ystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 bias voltage when left floating.
Pulldown
Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects
Pullup
CLK1, nCLK1 inputs. LVCMOS/LVTTL interface levels.
Output supply pin for Bank B outputs.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pins.
Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW,
31
SELB1
Input
Pullup
selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Power
Core supply pins.
32, 40
V
CC
Output enable pin. QB1/nQB1 outputs are enable.
33
OEB1
Input
Pullup
LVCMOS/LVTTL interface levels.
Output enable pin. QB0/nQB0 outputs are enabled.
34
OEB0
Input
Pullup
LVCMOS/LVTTL interface levels.
Power
Negative supply pins.
35, 43
V
EE
Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW,
36
SELB0
Input
Pullup
selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels.
When LOW, PLL is bypassed. When HIGH, PLL output is active.
38
nPLL_BYPASS_B
Input
Pullup
Output enable pin. QA1/nQA1 outpus are enabled.
41
OEA1
Input
Pullup
LVCMOS/LVTTL interface levels.
Output enable pin. QA0/nQA0 outputs are enabled.
OEA0
Input
Pullup
42
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT0 is the output,
45,
XTAL_OUT0,
Input
XTAL_IN0
XTAL_IN0 is the input.
46
47
CLK0
Input
Pulldown LVCMOS/LVTTL clock input.
Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects
48
IN_SELA
Input
Pullup
CLK0 input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
54.8°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.97
V
CC
– 0.22
2.97
Typical
3.3
3.3
3.3
Maximum
3.63
V
CC
3.63
165
22
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
CLK0, SELA0, SELA1
nPLL_BYPASS_A,
nPLL_BYPASS_B,
IN_SELA, IN_SELB,
SELB1, SELB0, OEB0,
OEB1, OEA0, OEA1
CLK0, SELA0, SELA1
nPLL_BYPASS_A,
nPLL_BYPASS_B,
IN_SELA, IN_SELB,
SELB1, SELB0, OEB0,
OEB1, OEA0, OEA1
V
CC
= V
IN
= 3.63V
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
I
IH
Input
High Current
V
CC
= V
IN
= 3.63V
5
µA
V
CC
= 3.63V, V
IN
= 0V
-5
µA
I
IL
Input
Low Current
V
CC
= 3.63V, V
IN
= 0V
-150
µA
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
3C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK1,
nCLK1
nCLK1
CL K1
Test Conditions
V
IN
= V
CC
= 3.63V
V
IN
= 0V, V
CC
= 3.63V
V
IN
= 0V, V
CC
= 3.63V
-150
-5
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage;
V
CMR
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
XTAL0
XTAL1
Test Conditions
Minimum
Typical
25
19.44
50
7
1
Maximum
Units
MHz
MHz
Ω
pF
mW
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
sk(b)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Bank Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
155.52MHz, (12kHz - 1.3MHz)
156.25MHz, (1.875MHz - 20MHz)
20% to 80%
250
0.6
0.7
600
Test Conditions
SELB0 = 1; OEB0 = 1
SELA0 = 0; OEA0 = 1
Minimum
Typical
155.52
156.25
60
Maximum
Units
MHz
MHz
ps
ps
ps
ps
%
odc
Output Duty Cycle
47
53
NOTE 1: Defined as skew within a bank of outputs at the same supply voltags and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: See Phase Noise plot.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843204AGI-01 REV. A OCTOBER 18, 2007
ICS843204I-01
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
2V
V
CC
,
V
CCO_A
,
V
CCO_B
V
CCA
Qx
SCOPE
V
CC
nCLK1
LVPECL
nQx
V
EE
CLK1
V
PP
Cross Points
V
CMR
-1.3V ± 0.33V
V
EE
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
Phase Noise Plot
Noise Power
nQXx
QXx
Phase Noise Mask
nQXy
Offset Frequency
QXy
f
2
f
1
tsk(b)
Where X = A or B
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS P
HASE
J
ITTER
B
ANK
S
KEW
nQA0, nQA1
nQB0, nQB1
80%
QA0, QA1
QB0, QB1
t
PW
t
PERIOD
80%
V
SW I N G
Clock
Outputs
x 100%
20%
t
R
t
F
20%
odc =
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843204AGI-01 REV. A OCTOBER 18, 2007
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

ICS843204AGI-01T Related Products

ICS843204AGI-01T 843204AGI-01 843204AGI-01T ICS843204AGI-01
Description Clock Generator, 156.25MHz, PDSO48, 6.10 X 12.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-48 Clock Generator Clock Generator Clock Generator, 156.25MHz, PDSO48, 6.10 X 12.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-48
Is it Rohs certified? incompatible incompatible incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Reach Compliance Code compliant unknown unknown compliant

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