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NDS336PL99Z

Description
Small Signal Field-Effect Transistor, 1.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-3
CategoryDiscrete semiconductor    The transistor   
File Size84KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

NDS336PL99Z Overview

Small Signal Field-Effect Transistor, 1.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-3

NDS336PL99Z Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G3
Contacts3
Manufacturer packaging codeSUPERSOT
Reach Compliance Codeunknown
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage20 V
Maximum drain current (ID)1.2 A
Maximum drain-source on-resistance0.2 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G3
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeP-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal formGULL WING
Terminal locationDUAL
transistor applicationsSWITCHING
Transistor component materialsSILICON
June 1997
NDS336P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT
TM
-3 P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are needed
in a very small outline surface mount package.
Features
-1.2 A, -20 V, R
DS(ON)
= 0.27
@ V
GS
= -2.7 V
R
DS(ON)
= 0.2
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface
package.
Mount
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS336P
-20
±8
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
-1.2
-10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS336P Rev. E

NDS336PL99Z Related Products

NDS336PL99Z NDS336PS62Z NDS336PD87Z
Description Small Signal Field-Effect Transistor, 1.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-3 Small Signal Field-Effect Transistor, 1.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-3 Small Signal Field-Effect Transistor, 1.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-3
Maker Fairchild Fairchild Fairchild
Parts packaging code SOT SOT SOT
package instruction SMALL OUTLINE, R-PDSO-G3 SMALL OUTLINE, R-PDSO-G3 SMALL OUTLINE, R-PDSO-G3
Contacts 3 3 3
Manufacturer packaging code SUPERSOT SUPERSOT SUPERSOT
Reach Compliance Code unknown unknown unknown
ECCN code EAR99 EAR99 EAR99
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 20 V 20 V 20 V
Maximum drain current (ID) 1.2 A 1.2 A 1.2 A
Maximum drain-source on-resistance 0.2 Ω 0.2 Ω 0.2 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PDSO-G3 R-PDSO-G3 R-PDSO-G3
Number of components 1 1 1
Number of terminals 3 3 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type P-CHANNEL P-CHANNEL P-CHANNEL
Certification status Not Qualified Not Qualified Not Qualified
surface mount YES YES YES
Terminal form GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL
transistor applications SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON
Maximum operating temperature 150 °C 150 °C -
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