531NB866M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531NB866M000DGR

531NB866M000DGR: DescriptionLVDS Output Clock Oscillator, 866MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531NB866M000DGR Overview

LVDS Output Clock Oscillator, 866MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531NB866M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	866 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Infrared remote control circuit b

Three-phase rectifier speed regulating circuit

DC-DC conversion circuit 04

Current controlled square wave-triangular wave generator circuit diagram

Pulse sorting circuit

Door phone call circuit

Qt Learning Road 50 Custom Editable Model: [p=22, null, left][color=#555555][font=Tahoma, Helvetica, SimSun, sans-serif][size=14px][color=#333333][backcolor=rgb(247, 247, 247)][font=Tahoma, Arial, Helvetica, sans-serif]In the previous chapter,...; 兰博 Embedded System

i.MX8 Mini series chip core board (MYC-C8MMX) data sharing: In recent years, with the evolution of AIOT technology, powerful CPU performance, cost leadership, and long supply cycle embedded boards have become the general demand for hardware development of thes...; blingbling111 ARM Technology

【KW41Z】Requesting the cloud disk link of MCUXpresso: I have to use the official IDE. I have logged into the official website several times but my account was locked.Has anyone downloaded MCUXpresso before and can give me a cloud disk link? It is usually...; suoma NXP MCU

HDLC receiving project design help: I have a problem with the HDLC receiving program course design. 1. Should the schematic device buffer, SRAM and other devices be generated using VHDL language or can they be found in the software? 2. ...; 通过考试 FPGA/CPLD

I don't know, please explain.: #include "msp430g2553.h" const unsigned int spwm[] = {250, 327, 396, 452, 487, 499, 487, 452, 396, 327,250, 172, 103, 47, 12, 3, 12, 47, 103, 172,};unsigned int n=0;void TimerA_PWM()//产生PWM波{P1DIR |= ...; cengyu3 Programming Basics

The seven most downloaded classic FPGA books: [align=center][/align] [url=https://www.eeworld.com.cn/a16621][size=5][b]FPGA Application Development Introduction and Typical Examples[/b][/size][/url] [align=left]This book starts with the history o...; 高进 Download Centre

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components