4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches
Ordering Information
Order
Number
FM3540CM14
FM3540CMT14
FM3540SM14
FM3540SMT14
FM3550CM16
FM3550CMT16
FM3550SM16
FM3550SMT16
FM3560M20
FM3560MT20
Note About Y-Port Output Type:
FM3560 device has a dedicated input pin (LEVEL) to select either "Fixed 2.5Volts" or "Open-Collector" Y-Port output type.
Note About Device Address:
1. For FM3540 or FM3550 with an alternate device address of 0110111, contact Fairchild Marketing/Sales.
2. FM3560 device has a dedicated input pin (ASEL) to select either "1001110" or 0110111" as device address.
Package
Number
M14A
MTC14
M14A
MTC14
M16A
MTC16
M16A
MTC16
M20B
MTC20
Package
Description
14-Pin SO
14-Pin TSSOP
14-Pin SO
14-Pin TSSOP
16-Pin SO
16_Pin TSSOP
16-Pin SO
16-Pin TSSOP
20-Pin SO
20-Pin TSSOP
Packing
T&R
T&R
T&R
T&R
T&R
T&R
T&R
T&R
T&R
T&R
Y-Port
Output Type
Open-Collector
Open-Collector
Fixed 2.5V
Fixed 2.5V
Open-Collector
Open-Collector
Fixed 2.5V
Fixed 2.5V
(See Note below)
(See Note below)
Device
Address
1001110
1001110
1001110
1001110
1001110
1001110
1001110
1001110
(See Note below)
(See Note below)
Pin Connection Diagrams
14-Pin Packages
FM3540
SDA
I0
I1
I2
I3
I4
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SCL
VCC
Y0
Y1
Y2
Y3
Y4
16-Pin Package
FM3550
SCL
SDA
Override#
I0
I1
I2
I3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
WP
Non_Mux_Out
Mux_Sel
Y0
Y1
Y2
Y3
20-Pin Packages
FM3560
SCL
SDA
OVRD
I0
I1
I2
I3
I4
Level
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
ASEL
WP
Non_Mux_Out
MUXSEL
Y0
Y1
Y2
Y3
Y4
Pin Description
Pin Name
I[0:4]
Y[0:4]
SCL
Override#
WP
Non_Mux_Out
Mux_Sel
Level
ASEL
SDA
Description
Data Inputs w/Pullups (10K-40K)
O/D Data Outputs
Serial Port Clock Input (120K pullup)
Override Input, sets all outputs to 0
Write Protect Input
Non-Multiplexed Output
Mux. Select Input
Level Select Input
Address Select Input
Serial Port Data I/O (120K pullup)
2
FM3540/50/60 Rev. B
www.fairchildsemi.com
FM3540/50/60
4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches
Functional Description
The FM3550/60 is block diagram is show in Figure 1. The device
has two primary functional modes of operation and an additional
mode for programming the device.
Operational Modes
During standard operation the device will either pass an address
to the Y-Port from the I-Port or from an internally programmed
value. At power up the device will default to passing the I-Port
value to the Y-Port.
The I-port values are generated from the motherboard of the
system and may be hardwired or driven by another device. Pull-
up resistors are provided on the device to accommodate this
device being driven by open drain output drivers. The device
expects standard CMOS input signals. The level of the output
signal is determined by the Level input. If this input is connected
to Vss/Ground, the output is at 2.5V on the multiplexed outputs
(Y0-Y4). The non-multiplexed output is always at CMOS levels.
The Level input, if left unconnected (it has an internal pullup), will
cause the Y0-Y4 outputs to operate as open-drain outputs. The
override# input, when set to 0, will cause all the outputs to be set
to 0. The WP signal, if set to logic 1, will prevent data from being
written to the non-volatile register.
The mux_sel input, when set to logic 0, will select the data from the
non-volatile register to drive on the Y0-4 outputs. If set to logic 1,
the data from the inputs are selected instead. The non_mux_out
latch is transparent when the mux_sel signal is at logic 0, and will
latch data when the mux_select is in a logic 1 state.
Serial Output Port Register (SOPR)
(Address 000b and 001b)
MXSB MXSA
0
b7
0
b6
I5
b5
NMO
b4
Data Field
I3
b3
I2
b2
I1
B1
I0
b0
b7-b6 - Multiplexer Select Bits (MXSB,MXSA)
00 - Multiplexer passes the SOPR(A).
01 - Multiplexer passer the SOPR(B).
10 - Multiplexer defaults to passing the I-Port Value.
b5, b3-b0 - Data Field. New value to be output through the
multiplexer.
nmo - Non multiplexed output from internal non-volatile bit
Parallel Input Port Register (PIPR)
(Address 002b)
Address Field
0
b7
0
b6
0
b5
I4
b4
Data Field
I3
b3
I2
b2
I1
B1
I0
b0
b7-b5 - Address field. Value is always 000
b4-b0 - Data Field. Value is equal to the value on the I-Port.
The external Port Register captures the value on the I-Port. Data
is latched into this register on the first clock after a start condition
is seen. This insures that a valid value will always be in this register
if it is read. This register is a read only register with respect to the
IIC port.
Over-
ride#
0
0
1
1
mux_
sel MXSB MXSA
0
1
0
0
X
X
1
0
X
X
0
0
mux_outputs
all 0's
Mux_inputs
(see note 1)
Mux_inputs
(see note 1)
Non_
mux_output
all 0's
latched NMO
latched NMO
Output Port: Y0-Y4
The output port is an open drain output to allow for easy connec-
tion to devices running at different voltage levels. The port is
always active and either passes the value on the I-Port or the value
in the Serial output port Register (SOPR). Changing the Mux Path
is accomplished by writing to b7, b6 of the Serial Input Port
Register. SOPR-b7, b6 defaults to a value of "10" at power up and
the default path is from the I-Port through to the output port. The
multiplexer only updates when an IIC stop condition is observed.
Register Description
The FM3550/60 has 3 registers in total. These registers are made
up of a combination of read only, write only and read write bits. The
two registers are listed below.
From Non-
From non-
volatile reg-
volatile reg-
ister (SOPRA) ister (SOPRA)
Do not use this combination
From Non-
From non-
volatile reg-
volatile reg-
ister (SOPRB) ister (SOPRB)
Mux_inputs
From Non-
volatile reg-
ister (SOPRA
or SOPRB)
Serial Output Port Register A(SOPRA) Address: 00H
- A read/
write register that contains the new value to be written to output
Port-Y and the multiplexer select bit.
Serial Output Port Register B(SOPRB) Address: 01H
- A read/
write register that contains the new value to be written to output
Port-Y and the multiplexer select bit.
Parallel Input Port Register (PIPR) Address: 02H
- A read only
register that is loaded with the 5 bit value of the I-Port.
1
1
0
0
1
0
1
1
1
1
Note 2 Note 1
Note 1:
Latched NMO state will be the value present on the NMO output at the time
of the mux_sel input transitioning from logic 0 to logic 1 state.
Note 2:
Output depends on previously selected state of MXSB and MXSA bits
written to device.
3
FM3540/50/60 Rev. B
www.fairchildsemi.com
FM3540/50/60
4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches
Multiplexer Logic
The output multiplexer logic determines what value is actually
output to the Y-port. The value that is output is dependent upon b7-
b6 of the SOPRA and SOPRB registers, as well as the external
mux_sel and override# inputs. The is only one set of MXS bits in
the SOPRA and SOPRB registers. Regardless of whether one
writes to SOPRA or SOPRB register for setting the MXS bits, the
result is the same. These same bits appear in both the registers.
If the mux_sel is logic 0 and OVRD is logic 1, then, if b7,b6 is “10”
then the value on the I-port is passed. When b7 is “00” the value
of the SOPRA register is passed on the next IIC stop condition,
and .When b7 is “01” the value of the SOPRB register is passed
on the next IIC stop condition. If mux_sel is logic 1 and OVRD is
logic 1, the input lines I0-4 are used to drive the outputs. The above
table describes all the combinations.
If so desired only the SOPRA register can be read. This is
accomplished by issuing a stop command after acknowledge bit
for the first byte read. If no stop is issued, the device will output the
registers in the above sequence.
Writing to the Registers
Data is written to the SOPR registers through the serial port
interface. When a write request is received with the Start Address
it is assumed that the intent is to write the SOPR registers. The
value placed in the least 6 significant bits of the register contain the
new code to be placed in the SOPR A/B registers. The value of the
two most significant bits must contain the address of the destina-
tion register SOPRA or SOPRB.
The internal non-volatile latch takes about 10 ms to update its
data. The new data is reflected on the outputs after the internal
non-volatile latch is updated, if the corresponding select bits
(MXSx, OVRD and mux_sel) are set to reflect the state of the non-
volatile register
IIC Interface
The IIC Interface is a standard slave interface. As a slave interface
the device will not generate its own clock. Data can be read from
and written into the device. Commands for reading and writing the
registers are generated by the IIC Master.
Register Read Sequence
Slave
SOPRA
SOPRB
PIPR
S Address R A Register A Register A Register A P
S
1001110
1
A 00bbbbbb A 00bbbbbb A 00bbbbbb A P
START and STOP Conditions
SDA
Register Write Sequence
Slave
SOPRx
S Address W A Register A S
SCL
START
Condition
STOP
Condition
S
1001110
0
A xxbbbbbb
A S
xx = Register Selection bits (MXSB and MXSA) xx = 00 selects
SOPRA, 01 selects SOPRB
The IIC protocol uniquely defines START and STOP conditions.
A START condition is defined as a HIGH to LOW transition of the
SDA signal while SCL is HIGH. A STOP condition is defined as a
LOW to HIGH transition of the SDA signal while SCL is HIGH.
These are shown in Figure 2.
Register Write Sequence using
Repeated Start Condition
Slave
SOPRA
Slave
SOPRx
S Address R A Register A S Address W A Register A P
S 1001110 1 A 00bbbbbb A S 1001110 0
A xxbbbbbb A P
Device Addressing
The device uses 7 bit IIC addressing. The address has been
defined as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the
ASEL input is ‘0’. The address byte is the first byte of data sent after
a start condition. This is the only address that this device will
respond to. The device will not respond to the general call address
0000 000.
Figure 4
Reading from the Registers
Data can be read from both of the internal registers. All reads are
non-destructive and do not change the value in the register or the
internal state of the device. When a start condition is received with
a read request both registers can be read out in the following
sequence.
(1)
(2)
(3)
SOPRA - Serial Output Port Register A
SPORB - Serial Output Port Register B
PIPR - PORT-I Value
4
FM3540/50/60 Rev. B
www.fairchildsemi.com
FM3540/50/60
4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-STATED
Outputs Active (Note 2)
DC Input Diode Current (I
IK
) V
I
< 0V
DC Output Diode Current (IOK)
V
O
< 0V
V
O
> Vcc
DC Output Source/Sink Current (I
OH
/I
OL
)
DC Vcc or Ground Current per
Supply Pin (I
CC
or Ground)
Storage Temperature Range (T
STG
)
-0.5V to +6.5V
-0.5V to +6.5V
-0.5V to +6.5V
-0.5 to V
CC
+0.5V
-50mA
-50mA
+50mA
±50mA
±100mA
-65
°
C to +150
°
C
Recommended Operating Conditions
(Note 3)
Power Supply
Input Voltage
Output Voltage (V
O
)
Output Current I
OL
Free Air Operating Temperature(TA)
Minimum Input Edge Rate (d
T
/d
V
)
V
IN
= 0.8V to 2.0V, Vcc = 3.0V
3.0V to 5.5V
-0.3V to 5.5V
0V TO V
CC
3mA
-0°C to +70°C
10nS/V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the “Electrical Characteristics” table are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will
define the conditions for actual device operation.
Note 2:
IO Absolute Maximum Rating must be observed.
Note 3:
Floating or unused pins (inputs or I/O’s) must be held HIGH or LOW.
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