FUJITSU SEMICONDUCTOR
DATA SHEET
DS704-00003-0v01-E
16-bit Proprietary Microcontroller
CMOS
F MC-16FX MB96650 Series
MB96F656/F657*
DESCRIPTION
MB96650 series is based on FUJITSU’s advanced 16FX architecture (16-bit with instruction pipeline for
RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus
allowing for easy migration of 16LX Software to the new 16FX products.
16FX improvements compared to the previous generation include significantly improved performance -
even at the same operation frequency, reduced power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz resonator. The result is a minimum
instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is
minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree
allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.
*: These devices are under development and specification is preliminary.
These products under development may change its specification without notice.
Note: F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
2
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright
©
2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.7
MB96650 Series
FEATURES
Technology
0.18μm CMOS
CPU
F MC-16FX CPU
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of
pointers)
8-byte instruction execution queue
Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
2
System clock
On-chip PLL clock multiplier (×1 to ×8, ×1 when PLL stop)
4 MHz to 8 MHz external crystal oscillator clock
(maximum frequency when using ceramic resonator depends on Q-factor)
Up to 16 MHz external clock for devices with fast clock input feature
32.768 kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog
Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals
The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after
a Power or External reset
Low Power Consumption - 13 operating modes (different Run, Sleep, Timer modes, Stop mode)
On-chip voltage regulator
Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power
consumption figures
Low voltage reset
Reset is generated when supply voltage is below minimum
Code Security
Protects Flash Memory content from unintended read-out
DMA
Automatic transfer function independent of CPU, can be assigned freely to resources
Interrupts
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
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DS704-00003-0v01-E
MB96650 Series
CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
USART
Full duplex USARTs (SCI/LIN)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
Extended support for LIN-Protocol to reduce interrupt load
I
2
C
Up to 400 kbps
Master and Slave functionality, 7-bit and 10-bit addressing
A/D converter
SAR-type
8/10-bit resolution
Signals interrupt on conversion end, single conversion mode, continuous conversion mode,
stop conversion mode, activation by software, external trigger, reload timers and PPGs
Range Comparator Function
Scan Disable Function
Source Clock Timers
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
Hardware Watchdog Timer
Hardware watchdog timer is active after reset
Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
Reload Timers
16-bit wide
1
2
3
4
5
6
Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency
Event count function
Free Running Timers
Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4)
1
2
3
4
5
6
7
8
Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency
Input Capture Units
16-bit wide
Signals an interrupt upon external event
Rising edge, Falling edge or Both (rising&falling) edges sensitive
DS704-00003-0v01-E
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MB96650 Series
Output Compare Units
16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output signal
Programmable Pulse Generator
16-bit down counter, cycle and duty setting registers
Can be used as 2 × 8-bit PPG
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload
timer underflow as clock input
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
Start delay
Quadrature Position/Revolution Counter (QPRC)
Edge count mode, Phase count mode, Level count mode
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers with interrupt
Detection edge of the three external event input pins AIN, BIN and ZIN is configurable
Real Time Clock
Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)
Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
External Interrupts
Edge or Level sensitive
Interrupt mask and pending bit per channel
Each available CAN channel RX has an external interrupt for wake-up
Selected USART channels SIN have an external interrupt for wake-up
Non Maskable Interrupt
Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block
Once enabled, can not be disabled other than by reset
High or Low level sensitive
Pin shared with external interrupt 0
I/O Ports
Most of the external pins can be used as general purpose I/O
2
All push-pull outputs (except when used as I C SDA/SCL line)
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable input enable
One input level per GP-IO-pin (either Automotive or CMOS-Schmitt trigger)
Bit-wise programmable pull-up resistor
4
DS704-00003-0v01-E
MB96650 Series
Built-in OCD (On Chip Debugger)
One-wire debug tool interface
Break function:
- Hardware break: 6 points (shared with code event)
- Software break: 4096 points
Event function
- Code event: 6 points (shared with hardware break)
- Data event: 6 points
- Event sequencer: 2 levels
Execution time measurement function
Trace function: 42 branches
Security function
Flash Memory
Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank
Command sequencer for automatic execution of programming algorithm and for supporting DMA for
programming of the Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase
DS704-00003-0v01-E
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