PCF8594C-2
512
×
8-bit CMOS EEPROM with I
2
C-bus interface
Rev. 01 — 09 May 2002
Product data
1. Description
The PCF8594C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 4 kbits (512
×
8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I
2
C-bus. Up to four
PCF8594C-2 devices may be connected to the I
2
C-bus. Chip select is accomplished
by two address inputs (A1 and A2).
Timing of the E/W cycle is carried out internally, thus no external components are
required. Programming Time Control (PTC), Pin 7, must be connected to either V
DD
or left open-circuit. There is an option of using an external clock for timing the length
of an E/W cycle.
2. Features
s
Low power CMOS:
x
2.0 mA maximum operating current
x
maximum standby current 10
µA
(at 6.0 V), typical 4
µA
s
Non-volatile storage of 4 kbits organized as 512
×
8-bit
s
Single supply with full operation down to 2.5 V
s
On-chip voltage multiplier
s
Serial input/output I
2
C-bus
s
Write operations:
x
byte write mode
x
8-byte page write mode (minimizes total write time per byte)
s
Read operations:
x
sequential read
x
random read
s
Internal timer for writing (no external components)
s
Internal power-on reset
s
0 to 100 kHz clock frequency
s
High reliability by using a redundant storage code
s
Endurance: 1,000,000 Erase/Write (E/W) cycles at T
amb
= 22
°C
s
10 years non-volatile data retention time
Philips Semiconductors
PCF8594C-2
512
×
8-bit CMOS EEPROM with I
2
C-bus interface
s
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
s
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
s
Offered in DIP8 and SO8 packages.
3. Quick reference data
Table 1:
Symbol
V
DD
I
DDR
Quick reference data
Parameter
supply voltage
supply current read
f
SCL
= 100 kHz
V
DD
= 2.5 V
V
DD
= 6 V
I
DDW
supply current E/W
f
SCL
= 100 kHz
V
DD
= 2.5 V
V
DD
= 6 V
I
DD(stb)
standby supply current
V
DD
= 2.5 V
V
DD
= 6 V
-
-
-
-
-
-
-
-
0.6
2.0
3.5
10
mA
mA
µA
µA
-
-
-
-
60
200
µA
µA
Conditions
Min
2.5
Typ
-
Max
6.0
Unit
V
4. Ordering information
Table 2:
Ordering information
Package
North America
PCF8594C-2P
PCF8594C-2T
PCF8594C2N
PCF8594C2D
Name
DIP8
SO8
Description
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package 8 leads (straight);
body width 3.9 mm
Version
SOT97-1
SOT96-1
Type number
9397 750 09649
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 09 May 2002
2 of 20
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Product data
Rev. 01 — 09 May 2002
A2
A1
3
2
TEST MODE DECODER
VDD
8
4
002aaa258
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
9397 750 09649
5. Block diagram
Philips Semiconductors
PCF8594C-2
SCL
SDA
6
5
n
INPUT
FILTER
I
2
C-BUS CONTROL LOGIC
1
WP
BYTE
COUNTER
3
ADDRESS
SWITCH
SHIFT
REGISTER
BYTE
LATCH
(8 bytes)
ADDRESS
POINTER
ADDRESS
HIGH
REGISTER
SEQUENCER
DIVIDER
( 128)
8
EEPROM
4
EE
CONTROL
512
×
8-bit CMOS EEPROM with I
2
C-bus interface
TIMER
( 16)
7
PTC
POWER-ON-RESET
OSCILLATOR
PCF8594C-2
VSS
3 of 20
Fig 1. Block diagram.
Philips Semiconductors
PCF8594C-2
512
×
8-bit CMOS EEPROM with I
2
C-bus interface
7. Device addressing
Table 4:
Selection
Bit
Device
[1]
Device address code
Device code
b7
[1]
1
b6
0
b5
1
b4
0
b3
A2
Chip Enable
b2
A1
b1
A0
R/W
b0
R/W
The Most Significant Bit (MSB) ‘b7’ is sent first.
A2 and A1 are hardware selectable pins and A0 is sofware selectable pin.
A system could have up to four PCF8594C-2 devices on the same I
2
C-bus,
equivalent to a 16 kbit EEPROM or 4 devices of 512 bytes of memory.
A0 selects the lower (logic level ‘0’) or the higher (logic level ‘1’) 256-byte page on the
selected device. The device is selected by bits A2 and A1.
Figure 3
shows the various
address and page combinations.
I
2
C-BUS
PCF8594C-2
DEVICE 1
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
PCF8594C-2
DEVICE 2
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
PCF8594C-2
DEVICE 3
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
PCF8594C-2
DEVICE 4
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
002aaa260
A2
0
0
A1
0
0
A0
1
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
1
1
0
Fig 3. Device addressing.
9397 750 09649
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 09 May 2002
5 of 20
PCB Design
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