UJA1069
LIN fail-safe system basis chip
Rev. 04 — 28 October 2009
Product data sheet
1. General description
The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Local Interconnect
Network (LIN) interface. The fail-safe SBC supports all networking applications which
control various power and sensor peripherals by using LIN as a local sub-bus. The
fail-safe SBC contains the following integrated devices:
•
•
•
•
•
•
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
Advanced independent watchdog
Dedicated voltage regulator for microcontroller
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
•
•
•
•
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and sub-system levels
The UJA1069 is designed to be used in combination with a microcontroller and a LIN
controller. The fail-safe SBC ensures that the microcontroller is always started up in a
defined manner. In failure situations the fail-safe SBC will maintain the microcontroller
function for as long as possible, to provide full monitoring and software driven fall-back
operation.
The UJA1069 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
2. Features
2.1 General
I
Contains a full set of LIN ECU functions:
N
LIN transceiver
N
Voltage regulator for the microcontroller (5.0 V)
N
Enhanced window watchdog with on-chip oscillator
N
Serial Peripheral Interface (SPI) for the microcontroller
N
ECU power management system
N
Fully integrated autonomous fail-safe system
I
Designed for automotive applications:
N
Supports 14 V and 42 V architectures
N
Excellent ElectroMagnetic Compatibility (EMC) performance
N
±8
kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for
off-board pins
N
±4
kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins
N
±60
V short-circuit proof LIN-bus pin
N
Battery and LIN-bus pins are protected against transients in accordance with
ISO 7637-3
N
Very low sleep current
I
Supports remote flash programming via the LIN-bus
I
Available in:
N
Small 6.4 mm
×
7.8 mm HTSSOP24 package with low thermal resistance
N
Small 8 mm
×
11 mm HTSSOP32 package with low thermal resistance
2.2 LIN transceiver
I
LIN 2.0 and SAE J2602 compliant LIN transceiver
I
Enhanced error signalling and reporting
I
Downward compatible with LIN 1.3 and the TJA1020
2.3 Power management
I
I
I
I
I
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the LIN-bus
External voltage regulators can easily be incorporated in the power supply system
(flexible and fail-safe)
I
42 V battery related high-side switch for driving external loads such as relays and
wake-up switches
I
Intelligent maskable interrupt output
UJA1069_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 28 October 2009
2 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
2.4 Fail-safe features
I
Safe and predictable behavior under all conditions
I
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,
guaranteeing autonomous fail-safe system supervision
I
Fail-safe coded 16-bit SPI interface for the microcontroller
I
Global enable pin for the control of safety-critical hardware
I
Detection and detailed reporting of failures:
N
On-chip oscillator failure and watchdog alerts
N
Battery and voltage regulator undervoltages
N
LIN-bus failures (short-circuits)
N
TXDL and RXDL clamping situations and short-circuits
N
Clamped or open reset line
N
SPI message errors
N
Overtemperature warning
I
Rigorous error handling based on diagnostics
I
Supply failure early warning allows critical data to be stored
I
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
I
Reporting in a single SPI message; no assembly of multiple SPI frames needed
I
Limp-home output signal for activating application hardware in case system enters
Fail-safe mode (e.g. for switching on warning lights)
I
Fail-safe coded activation of Software development mode and Flash mode
I
Unique SPI readable device type identification
I
Software-initiated system reset
3. Ordering information
Table 1.
Ordering information
Package
Name
UJA1069TW
UJA1069TW24
HTSSOP32
HTSSOP24
Description
Version
plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
plastic thermal enhanced thin shrink small outline package; 24 leads; SOT864-1
body width 4.4 mm; lead pitch 0.65 mm; exposed die pad
Type number
UJA1069_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 28 October 2009
3 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
4. Block diagram
SENSE
BAT42
BAT14
31 (23)
32 (24)
27 (19)
BAT
MONITOR
V1
(3) 4
V1
SYSINH
V3
INH/LIMP
29 (21)
30 (22)
17 (13)
UJA1069
INH
V1 MONITOR
INTN
WAKE
TEST
7 (6)
18 (14)
16 (12)
CHIP
TEMPERATURE
SBC
FAIL-SAFE
SYSTEM
WATCHDOG
(5) 6
(7) 8
WAKE
RESET/EN
RSTN
EN
SCK
SDI
SDO
SCS
11 (10)
9 (8)
10 (9)
12 (11)
SPI
OSCILLATOR
RTLIN
LIN
TXDL
RXDL
GND
26 (18)
25 (17)
3 (2)
5 (4)
23 (15)
BAT42
001aad669
LIN
The pin numbers in parenthesis are for the UJA1069TW24 version.
Fig 1.
Block diagram
UJA1069_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 28 October 2009
4 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
5. Pinning information
5.1 Pinning
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
1
2
3
4
5
6
7
8
9
32 BAT42
31 SENSE
30 V3
29 SYSINH
28 n.c.
27 BAT14
26 RTLIN
25 LIN
24 n.c.
23 GND
22 n.c.
21 n.c.
20 n.c.
19 n.c.
18 WAKE
17 INH/LIMP
001aad676
UJA1069TW
SDO 10
SCK 11
SCS 12
n.c. 13
n.c. 14
n.c. 15
TEST 16
Fig 2.
Pin configuration (HTSSOP32)
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
1
2
3
4
5
6
7
8
9
24 BAT42
23 SENSE
22 V3
21 SYSINH
20 n.c.
19 BAT14
18 RTLIN
17 LIN
16 n.c.
15 GND
14 WAKE
13 INH/LIMP
001aad677
UJA1069TW24
SCK 10
SCS 11
TEST 12
Fig 3.
Pin configuration (HTSSOP24)
UJA1069_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 28 October 2009
5 of 64
京公网安备 11010802033920号
EEWORLD
