The HS-1135RH features user programmable output clamps
to limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
H
and V
L
terminals (pins 8 and 5)
of the amplifier. V
H
sets the upper output limit, while V
L
sets
the lower clamp level. If the amplifier tries to drive the output
above V
H
, or below V
L
, the clamp circuitry limits the output
voltage at V
H
or V
L
( the clamp accur cy), respectively. The
a
low input bias currents of the clamp pins allow them to be
driven by simple resistive divider circuits, or active elements
such as amplifiers or DACs.
the clamp inputs floating. A similar description applies to the
symmetrical low clamp circuitry controlled by V
L
.
When the output is clamped, the negative input continues to
source a slewing current (I
CLAMP
) in an attempt to force the
output to the quiescent voltage defined by the input. Q
P5
must
sink this current while clamping, because the -IN current is
always mirrored onto the high impedance node. The clamping
current is calculated as (V
-IN
- V
OUT
)/R
F
. As an example, a
unity gain circuit with V
IN
= 2V, V
H
= 1V, and R
F
= 510Ω would
have I
CLAMP
= (2-1)/510Ω = 1.96mA. Note that I
CC
will
increase by I
CLAMP
when the output is clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to V
H
or V
L
. Offset errors, mostly due to V
BE
mismatches, necessitate a clamp accuracy parameter which is
found in the device specifications. Clamp accuracy is a function
of the clamping conditions. Referring again to Figure 1, it can
be seen that one component of clamp accuracy is the V
BE
mismatch between the Q
X6
transistors, and the Q
X5
transistors.
If the transistors always ran at the same current level there
would be no V
BE
mismatch, and no contribution to the
inaccuracy. The Q
X6
transistors are biased at a constant
current, but as described earlier, the current through Q
X5
is
equivalent to I
CLAMP
. V
BE
increases as I
CLAMP
increases,
causing the clamped output voltage to increase as well. I
CLAMP
is a function of the overdrive level (V
-IN
-V
OUTCLAMPED
) and
R
F
, so clamp accuracy degrades as the overdrive increases, or
as R
F
decreases. As an example, the specified accuracy of
±60mV
for a 2X overdrive with R
F
= 510Ω degrades to
±220mV
for R
F
= 240Ω at the same overdrive, or to
±250mV
for a 3X
overdrive with R
F
= 510Ω.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The
“Nonlinearity Near Clamp Voltage” curve in the data sheet
illustrates the impact of several clamp levels on linearity.
Clamp Circuitry
Figure 1 shows a simplified schematic of the HS-1135RH
input stage, and the high clamp (V
H
) circuitry. As with all
current feedback amplifiers, there is a unity gain buffer (Q
X1
- Q
X2
) between the positive and negative inputs. This buffer
forces -IN to track +IN, and sets up a slewing current of (V
-
IN
- V
OUT
)/R
F
. This current is mirrored onto the high
impedance node (Z) by Q
X3
-Q
X4
, where it is converted to a
voltage and fed to the output via another unity gain buffer. If
no clamping is utilized, the high impedance node may swing
within the limits defined by Q
P4
and Q
N4
. Note that when the
output reaches it’s quiescent value, the current flowing
through -IN is reduced to only that small current (-I
BIAS
)
required to keep the output at the final voltage.
V+
Q
P3
Q
P4
50K
(30K
FOR V
L
)
Z
+1
V
H
Q
N5
Q
P2
Q
P5
Q
N6
Q
P6
Q
N4
200Ω
Q
N2
Q
P1
+IN
V-
V+
Q
N1
I
CLAMP
R
1
Clamp Range
Unlike some competitor devices, both V
H
and V
L
have usable
ranges that cross 0V. While V
H
must be more positive than V
L
,
both may be positive or negative, within the range restrictions
indicated in the specifications. For example, the HS-1135RH
could be limited to ECL output levels by setting V
H
= -0.8V and
V
L
= -1.8V. V
H
and V
L
may be connected to the same voltage
(GND for instance) but the result won’t be in a DC output
voltage from an AC input signal. A 150 - 200mV AC signal will
still be present at the output.
Q
N3
V-
-IN
R
F
(EXTERNAL)
V
OUT
FIGURE 1. HS-1135RH SIMPLIFIED V
H
CLAMP CIRCUITRY
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base + 2V
BE
(QP5 and
QN5). Thus, QP5 clamps node Z whenever Z reaches V
H
.
R1 provides a pull-up network to ensure functionality with
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (V
CLAMP
/A
VCL
) the amplifier will
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HS-1135RH’s
2
HS-1135RH
subnanosecond recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 4.0ns
for the unclamped pulse, and 4.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed. Note:
The propagation delay illustrated is dominated by the
fixturing. The delta shown is accurate, but the true
HS-1135RH propagation delay is 500ps.
The layout and schematic of the board are shown here:
V
H
1
+IN
V
L
OUT
V+
V-
GND
Use of Die in Hybrid Applications
This amplifier is designed with compensation to negate the
package parasitics that typically lead to instabilities. As a
result, the use of die in hybrid applications results in
overcompensated performance due to lower parasitic
capacitances. Reducing R
F
below the recommended values
for packaged units will solve the problem. For A
V
= +2 the
recommended starting point is 300Ω, while unity gain
applications should try 400Ω.
FIGURE 2A. TOP LAYOUT
PC Board Layout
The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input. The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to pin 2, and connections to pin 2 should
be kept as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 2.
500Ω
FIGURE 2B. BOTTOM LAYOUT
500Ω
V
H
1
8
7
50Ω
6
5
GND
-5V
GND
OUT
V
L
0.1µF
10µF
+5V
50Ω
IN
2
3
4
10µF
0.1µF
FIGURE 2C. SCHEMATIC
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
Evaluation Board
An evaluation board is available for the HS-1135RH,
(HFA11XXEVAL). Please contact your local sales office for
information.
3
HS-1135RH
Burn-In Circuit
HS-1135RH CERDIP
R
2
R
1
R
1
D
2
V-
D
1
C
1
1
2
3
4
8
D
2
V+
C
1
D
1
+
-
7
6
5
NOTES:
1. R
1
= 1kΩ,
±5%
(Per Socket)
2. R
2
= 10kΩ,
±5%
(Per Socket)
3. C
1
= 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
4. D
1
= 1N4002 or Equivalent (Per Board)
5. D
2
= 1N4002 or Equivalent (Per Socket)
6. V+ = +5.5V
±0.5V
7. V- = -5.5V
±0.5V
Irradiation Circuit
HS-1135RH CERDIP
R
2
R
1
R
1
V-
C
2
1
2
3
4
8
+
-
7
6
5
C
1
V+
NOTES:
8. R
1
= 1kΩ,
±5%
9. R
2
= 10kΩ,
±5%
10. C
1
= C
2
= 0.01µF
11. V+ = +5.0V
±0.5V
12. V- = -5.0V
±0.5V
4
HS-1135RH
Die Characteristics
DIE DIMENSIONS:
59 mils x 58.2 mils x 19 mils
±1
mil
1500µm x 1480µm x 483µm
±25.4µm
INTERFACE MATERIALS:
Glassivation:
Type: Nitride
Thickness: 4k
Å
±0.5k
Å
Top Metallization:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k
Å
±0.4k
Å
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k
Å
±0.8k
Å
Substrate:
UHF-1, Bonded Wafer, DI
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Floating
ADDITIONAL INFORMATION:
Worst Case Current Density:
< 2 x 10
5
A/cm
2
Transistor Count:
89
Metallization Mask Layout
HS-1135RH
-IN
V
H
V+
OUT
+IN
V-
V
L
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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