74HC590
8-bit binary counter with output register; 3-state
Rev. 02 — 28 April 2009
Product data sheet
1. General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low
power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The
storage register has parallel (Q0 to Q7) outputs. The binary counter features a master
reset counter (MRC) and count enable (CE) inputs. The counter and storage register have
separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are
connected together, the counter state always is one count ahead of the register. Internal
circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided
for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of
the second stage. Cascading for larger count chains can be accomplished by connecting
RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks
are connected together, the counter state always is one count ahead of the register.
2. Features
I
I
I
I
I
Counter and register have independent clock inputs
Counter has master reset
Complies with JEDEC standard no. 7A
Multiple package options
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 2000 V
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Temperature range Name
74HC590N
74HC590D
74HC590PW
74HC590BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP16
SO16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
Version
SOT38-4
SOT403-1
SOT763-1
Type number Package
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 16 terminals; body
2.5
×
3.5
×
0.85 mm
NXP Semiconductors
74HC590
8-bit binary counter with output register; 3-state
5. Pinning information
5.1 Pinning
74HC590
terminal 1
index area
Q2
2
3
4
5
6
7
8
GND
RCO
001aac547
16 V
CC
15 Q0
14 OE
13 CPR
12 CE
11 CPC
10 MRC
9
74HC590
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aaj535
Q3
Q4
16 V
CC
15 Q0
14 OE
13 CPR
12 CE
11 CPC
10 MRC
9
RCO
1
2
3
4
5
6
7
8
001aac564
Q5
74HC590
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
16 V
CC
15 Q0
14 OE
13 CPR
12 CE
11 CPC
10 MRC
9
RCO
Q6
Q7
GND
(1)
Transparent top view
(1) The die substrate is attached to
the exposed die pad using
conductive die attach material. It
can not be used as a supply pin
or input.
Fig 5.
Pin configuration DIP16
Fig 6.
Pin configuration SO16
and TSSOP16
Fig 7.
Pin configuration
DHVQFN16
5.2 Pin description
Table 2.
Symbol
Q0 to Q7
GND
RCO
MRC
CPC
CE
CPR
OE
V
CC
Pin description
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
ripple carry output (active LOW)
master reset counter input (active LOW)
counter clock input (active HIGH)
count enable input (active LOW)
register clock input (active HIGH)
output enable input (active LOW)
supply voltage
74HC590_2
Product data sheet
Rev. 02 — 28 April 2009
1
Q1
© NXP B.V. 2009. All rights reserved.
4 of 21
NXP Semiconductors
74HC590
8-bit binary counter with output register; 3-state
6. Functional description
Table 3.
Inputs
OE
H
L
X
X
X
X
X
X
[1]
Function table
[1] [2]
Description
CPR
X
X
↑
↓
X
X
X
X
MRC
X
X
X
X
L
H
H
H
CE
X
X
X
X
X
L
L
H
CPC
X
X
X
X
X
↑
↓
X
Q outputs disable
Q outputs enable
counter data stored into register
register stage is not changed
counter clear
advance one count
no count
no count
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition.
RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter).
[2]
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
5 of 21
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