PSD4235G2V90UT datasheet, PDF - EEWORLD Datasheet

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PSD4235G2V90UT: DescriptionPIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size954KB，124 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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PSD4235G2V90UT Overview

PIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80

PSD4235G2V90UT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	,
Contacts	80
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G80
JESD-609 code	e3/e4
Number of terminals	80
Package body material	PLASTIC/EPOXY
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
surface mount	YES
Terminal surface	MATTE TIN/NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

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PSD4235G2V

Flash in-system programmable (ISP) peripherals

for 16-bit MCUs (3.3 V supply)

Features

PSD provides an integrated solution to 16-bit

MCU based applications that includes

configurable memories, PLD logic and I/Os:

■

Dual bank Flash memories

– 4 Mbit of Primary Flash memory (8 uniform

sectors, 32K x 16)

– 256 Kbit Secondary Flash memory with 4

sectors

– Concurrent operation: read from one

memory while erasing and writing the other

64 Kbit SRAM

PLD with macrocells

– Over 3000 gates of PLD: CPLD and DPLD

– CPLD with 16 output macrocells (OMCs)

and 24 input macrocells (IMCs)

– DPLD - user defined internal chip select

decoding

■

Seven I/O ports with 52 I/O pins

– 52 individually configurable I/O port pins

that can be used for the following functions:

– MCU I/Os

– PLD I/Os

– Latched MCU address output

– Special function l/Os

– l/O ports may be configured as open-drain

outputs

LQFP80 (U)

80-lead, Thin, Quad, Flat

■

Page register

– Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

Programmable power management

High endurance

– 100,000 Erase/write cycles of Flash

memory

– 1,000 Erase/WRITE Cycles of PLD

– 15 Year Data Retention

Single supply voltage

– 3.3 V ±10%

Memory speed

– 90 ns Flash memory and SRAM access

time

Package is ECOPACK

■

In-system programming (ISP) with JTAG

– Built-in JTAG compliant serial port allows

full-chip In-System Programmability

– Efficient manufacturing allow easy product

testing and programming

– Use low cost FlashLINK cable with PC

■

February 2009

Rev 2

1/124

www.st.com

Contents

PSD4235G2V

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1

In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1.1

1.1.2

1.1.3

First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 12

Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1

1.2.2

1.2.3

Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 13

Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3

PSDsoft™ Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ISP via JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PSD register description and address offsets . . . . . . . . . . . . . . . . . . . 22

5.1

5.2

5.3

5.4

5.5

5.6

Data-In registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . 24

Data-out registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . 24

Direction registers - ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . 24

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Drive registers - Ports C and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/124

PSD4235G2V

Contents

5.7

5.8

5.9

5.10

5.11

5.12

5.13

5.14

5.15

5.16

5.17

5.18

5.19

Enable-Out registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Input macrocells registers- ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1

6.2

Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Primary Flash memory and secondary Flash memory description . . . . . 32

6.2.1

6.2.2

Memory block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3

Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Toggle flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Error flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Erase timeout flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . 38

7.8

7.9

7.10

Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3/124

Contents

PSD4235G2V

8.1

8.2

8.3

Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1

9.2

9.3

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.1

10.2

10.3

Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12.1

12.2

12.3

12.4

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Memory Select configuration for MCUs with separate

Program and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

80C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12.5

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

17.1

17.2

17.3

Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 59

4/124

PSD4235G2V

Contents

17.4

17.5

17.6

17.7

The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

18.1

18.2

18.3

18.4

18.5

18.6

18.7

18.8

18.9

PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 66

Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

18.10 C16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

19.1

19.2

19.3

19.4

General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

19.5

19.6

19.7

19.8

19.9

PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

19.10 MCU Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

19.11 Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

19.12 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

19.13 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

19.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

19.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

19.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5/124

PSD4235G2V90UT Related Products

	PSD4235G2V90UT	PSD4235G290UIT	PSD4235G2V90UIT	PSD4235G2V12UIT	PSD4235G2V12UT
Description	PIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80	PIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80	PIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80	PIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80	PIA-GENERAL PURPOSE, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics
Parts packaging code	QFP	QFP	QFP	QFP	QFP
Contacts	80	80	80	80	80
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
JESD-30 code	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80
JESD-609 code	e3/e4	e3/e4	e3/e4	e3/e4	e3/e4
Number of terminals	80	80	80	80	80
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	260	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES	YES	YES
Terminal surface	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN/NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE

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About MSP430F5529 download program error: I downloaded a MSP430F5529 LCD program from the Internet. There was no problem compiling it in CCS, but when I downloaded it to the board, this error appeared. I don't quite understand. My board and t...; tei333 Microcontroller MCU

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Who has the USB driver for wce: I am now writing a USB driver under wce, written in EVC. I have searched for many days but still have no clue. My USB function is mainly to send commands from the upper computer to the lower computer,...; dayu1994 Embedded System

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