PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
Rev. 05 — 15 September 2008
Product data sheet
1. General description
The PCA9535 and PCA9535C are 24-pin CMOS devices that provide 16 bits of General
Purpose parallel Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and was
developed to enhance the NXP Semiconductors family of I
2
C-bus I/O expanders. The
improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, and smaller packaging. I/O expanders provide a simple
solution when additional I/O is needed for ACPI power switches, sensors, push buttons,
LEDs, fans, etc.
The PCA9535 and PCA9535C consist of two 8-bit Configuration (Input or Output
selection), Input, Output and Polarity Inversion (active HIGH or active LOW operation)
registers. The system master can enable the I/Os as either inputs or outputs by writing to
the I/O configuration bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
Inversion register. All registers can be read by the system master. Although pin-to-pin and
I
2
C-bus address compatible with the PCF8575, software changes are required due to the
enhancements and are discussed in
Application Note AN469.
The PCA9535 is identical to the PCA9555 except for the removal of the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW.
The PCA9535C is identical to the PCA9535 except that all the I/O pins are
high-impedance open-drain outputs.
The PCA9535 and PCA9535C open-drain interrupt output is activated when any input
state differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The fixed I
2
C-bus address of the PCA9535
and PCA9535C are the same as the PCA9555 allowing up to eight of these devices in any
combination to share the same I
2
C-bus/SMBus.
2. Features
I
I
I
I
I
I
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
NXP Semiconductors
PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
I
I
I
I
I
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Offered in four different packages: SO24, TSSOP24, HVQFN24 and HWQFN24
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9535D
PCA9535PW
PCA9535BS
PCA9535HF
PCA9535CD
SO24
TSSOP24
HVQFN24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
Version
SOT137-1
Type number
plastic thin shrink small outline package; 24 leads; body SOT355-1
width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
×
4
×
0.85 mm
SOT616-1
HWQFN24 plastic thermal enhanced very very thin quad flat
SOT994-1
package; no leads; 24 terminals; body 4
×
4
×
0.75 mm
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
PCA9535CPW TSSOP24
PCA9535CHF
plastic thin shrink small outline package; 24 leads; body SOT355-1
width 4.4 mm
HWQFN24 plastic thermal enhanced very very thin quad flat
SOT994-1
package; no leads; 24 terminals; body 4
×
4
×
0.75 mm
3.1 Ordering options
Table 2.
PCA9535D
PCA9535PW
PCA9535BS
PCA9535HF
PCA9535CD
PCA9535CPW
PCA9535CHF
Ordering options
Topside mark
PCA9535D
PCA9535PW
9535
P35H
PCA9535CD
PCA9535C
P35C
Temperature range
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
Type number
PCA9535_PCA9535C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 15 September 2008
2 of 31
NXP Semiconductors
PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
4. Block diagram
PCA9535
PCA9535C
A0
A1
A2
write pulse
read pulse
I
2
C-BUS/SMBus
CONTROL
SCL
SDA
INPUT
FILTER
8-bit
INPUT/
OUTPUT
PORTS
8-bit
INPUT/
OUTPUT
PORTS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
DD
write pulse
read pulse
POWER-ON
RESET
V
DD
V
SS
INT
002aac217
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9535; PCA9535C
PCA9535_PCA9535C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 15 September 2008
3 of 31
NXP Semiconductors
PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
5. Pinning information
5.1 Pinning
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aac214
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aac215
PCA9535D
PCA9535CD
PCA9535PW
PCA9535CPW
IO0_6 10
IO0_7 11
V
SS
12
IO0_6 10
IO0_7 11
V
SS
12
Fig 2.
Pin configuration for SO24
Fig 3.
Pin configuration for TSSOP24
PCA9535HF
PCA9535CHF
21 V
DD
20 SDA
PCA9535BS
20 SDA
19 SCL
21 V
DD
24 A2
24 A2
23 A1
terminal 1
index area
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
IO1_0 10
IO1_1 11
IO1_2 12
7
8
9
22 INT
terminal 1
index area
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
19 SCL
18 A0
17 IO1_7
16 IO1_6
15 IO1_5
14 IO1_4
13 IO1_3
IO1_2 12
002aac880
18 A0
17 IO1_7
16 IO1_6
15 IO1_5
14 IO1_4
13 IO1_3
22 INT
V
SS
9
23 A1
IO1_0 10
IO0_6
IO0_7
002aac216
Transparent top view
Transparent top view
Fig 4.
Pin configuration for HVQFN24
Fig 5.
Pin configuration for HWQFN24
PCA9535_PCA9535C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 15 September 2008
IO1_1 11
7
IO0_6
IO0_7
V
SS
8
4 of 31
NXP Semiconductors
PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
SO24, TSSOP24
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
SS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
A0
SCL
SDA
V
DD
[1]
Description
HVQFN24,
HWQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
address input 0
serial clock line
serial data line
supply voltage
supply ground
port 1 input/output
[2]
interrupt output (open-drain)
address input 1
address input 2
port 0 input/output
[2]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HVQFN24 and HWQFN24 package die supply ground is connected to both the V
SS
pin and the exposed
center pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
PCA9535 I/Os are totem pole, whereas the I/Os on PCA9535C are open-drain.
[2]
PCA9535_PCA9535C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 15 September 2008
5 of 31
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