PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt
and reset
Rev. 6 — 6 February 2013
Product data sheet
1. General description
The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General
Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for
I
2
C-bus/SMBus applications and was developed to enhance the NXP Semiconductors
family of I
2
C-bus I/O expanders. I/O expanders provide a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection),
input, output and polarity inversion (active HIGH or active LOW operation) registers. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with the Polarity inversion
register. All registers can be read by the system master.
The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the
internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are
held LOW, replacement of A2 with RESET and a different address range.
The PCA9539; PCA9539R open-drain interrupt output is activated when any input state
differs from its corresponding input port register state and is used to indicate to the system
master that an input state has changed.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCA9539, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I
2
C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to V
DD
. In the PCA9539R however, only the device state machine is
initialized by the RESET pin and the internal general-purpose registers remain
unchanged. Using the PCA9539R RESET pin will only reset the I
2
C-bus interface should
it be stuck LOW to regain access to the I
2
C-bus. This allows the I/O pins to retain their last
configured state so that they can keep any lines in their previously defined state and not
cause system errors while the I
2
C-bus is being restored.
Two hardware pins (A0, A1) vary the fixed I
2
C-bus address and allow up to four devices to
share the same I
2
C-bus/SMBus.
2. Features and benefits
16-bit I
2
C-bus GPIO with interrupt and reset
Operating power supply voltage range of 2.3 V to 5.5 V
(5.0 V
10 % for PCA9539PW/Q900 AEC-Q100 compliant devices)
5 V tolerant I/Os
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Polarity inversion register
Active LOW interrupt output
Active LOW reset input
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Offered in three different packages: SO24, TSSOP24, and HVQFN24
3. Ordering information
Table 1.
Ordering information
Topside
marking
9539
539R
PCA9539D
PCA9539PW
PCA9539PW
PA9539RPW
Package
Name
Description
Version
SOT616-1
SOT137-1
SOT355-1
HVQFN24 plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
4
0.85 mm
SO24
TSSOP24
plastic small outline package; 24 leads;
body width 7.5 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Type number
PCA9539BS
PCA9539RBS
PCA9539D
PCA9539PW
PCA9539PW/Q900
[1]
PCA9539RPW
[1]
PCA9539PW/Q900 is AEC-Q100 compliant. Contact
ics.support@nxp.com
for PPAP.
3.1 Ordering options
Table 2.
Ordering options
Orderable part number
Package
Packing method
Minimum
order
quantity
1500
6000
6000
1200
1000
Temperature
Type number
PCA9539BS
PCA9539BS,115
PCA9539BS,118
HVQFN24
HVQFN24
HVQFN24
SO24
SO24
Reel pack, SMD,
7-inch
Reel pack, SMD,
13-inch
Reel pack, SMD,
13-inch
Tube, bulk pack
Reel pack, SMD,
13-inch
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
PCA9539RBS
PCA9539D
PCA9539RBS,118
PCA9539D,112
PCA9539D,118
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
2 of 37
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Table 2.
Ordering options
…continued
Orderable part number
Package
Packing method
Minimum
order
quantity
1575
2500
2500
2500
Temperature
Type number
PCA9539PW
PCA9539PW,112
PCA9539PW,118
TSSOP24
TSSOP24
TSSOP24
TSSOP24
Tube, bulk pack
Reel pack, SMD,
13-inch
Reel pack, SMD,
13-inch
Reel pack, SMD,
13-inch
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
T
amb
=
40 C
to +85
C
PCA9539PW/Q900
PCA9539RPW
PCA9539PW/Q900,118
PCA9539RPW,118
4. Block diagram
PCA9539
PCA9539R
A0
A1
write pulse
read pulse
I
2
C-BUS/SMBus
CONTROL
SCL
SDA
INPUT
FILTER
8-bit
INPUT/
OUTPUT
PORTS
8-bit
INPUT/
OUTPUT
PORTS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
DD
write pulse
read pulse
POWER-ON
RESET
V
DD
RESET
V
SS
LP
FILTER
INT
002aad722
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9539; PCA9539R
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
3 of 37
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
INT
A1
RESET
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aad719
INT
A1
RESET
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
PCA9539D
PCA9539PW
PCA9539PW/Q900
PCA9539RPW
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
IO0_6 10
IO0_7 11
V
SS
12
IO0_6 10
IO0_7 11
V
SS
12
002aad720
Fig 2.
Pin configuration for SO24
Fig 3.
PCA9539BS
PCA9539RBS
24 RESET
20 SDA
23 A1
Pin configuration for TSSOP24
terminal 1
index area
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
19 SCL
18 A0
17 IO1_7
16 IO1_6
15 IO1_5
14 IO1_4
13 IO1_3
IO1_2 12
002aad721
IO1_0 10
21 V
DD
22 INT
V
SS
9
Transparent top view
Fig 4.
Pin configuration for HVQFN24
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
IO1_1 11
7
IO0_6
IO0_7
8
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
4 of 37
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
5.2 Pin description
Table 3.
Symbol
INT
A1
RESET
Pin description
Pin
SO24, TSSOP24
1
2
3
HVQFN24
22
23
24
interrupt output (open-drain)
address input 1
active LOW reset input. Driving this pin LOW
causes:
Description
•
•
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
SS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
A0
SCL
SDA
V
DD
[1]
PCA9539 to reset its state machine and
registers
PCA9539R to reset its state machine, but
has no effect on its registers
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
port 0 input/output 0
port 0 input/output 1
port 0 input/output 2
port 0 input/output 3
port 0 input/output 4
port 0 input/output 5
port 0 input/output 6
port 0 input/output 7
supply ground
port 1 input/output 0
port 1 input/output 1
port 1 input/output 2
port 1 input/output 3
port 1 input/output 4
port 1 input/output 5
port 1 input/output 6
port 1 input/output 7
address input 0
serial clock line input
serial data line open-drain input/output
supply voltage
HVQFN24 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
5 of 37
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