SMJ320C25, SMJ320C25 50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
D
Military Temperature Range
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
– –55°C to 125°C
100-ns or 80-ns Instruction Cycle Times
544 Words of Programmable On-Chip Data
RAM
4K Words of On-Chip Program ROM
128K Words of Data/Program Space
16 Input and 16 Output Channels
16-Bit Parallel Interface
Directly Accessible External Data Memory
Space
– Global Data Memory Interface
16-Bit Instruction and Data Words
16
×
16-Bit Multiplier With a 32-Bit Product
32-Bit ALU and Accumulator
Single-Cycle Multiply/Accumulate
Instructions
0 to 16-Bit Scaling Shifter
Bit Manipulation and Logical Instructions
Instruction Set Support for Floating-Point
Operations, Adaptive Filtering, and
Extended-Precision Arithmetic
Block Moves for Data/Program
Management
Repeat Instructions for Efficient Use of
Program Space
Eight Auxiliary Registers and Dedicated
Arithmetic Unit for Indirect Addressing
Serial Port for Direct Code Interface
Synchronization Input for Synchronous
Multiprocessor Configurations
Wait States for Communication to
Slow-Off-Chip Memories/Peripherals
On-Chip Timer for Control Operations
Three External Maskable User Interrupts
Input Pin Polled by Software Branch
Instruction
1.6-µm CMOS Technology
Programmable Output Pin for Signaling
External Devices
D
Single 5-V Supply
D
On-Chip Clock Generator
D
Packaging:
– 68-Pin Leaded Ceramic Chip Carrier (FJ
Suffix)
– 68-Pin Ceramic Grid Array (GB Suffix)
– 68-Pin Leadless Ceramic Chip Carrier
(FD Suffix)
68-Pin FJ and FD Packages
(Top View)
READY
CLKR
CLKX
V CC
V CC
IACK
MSC
CLKOUT1
CLKOUT2
XF
HOLDA
DX
FSX
X2 CLKIN
X1
BR
STRB
R/W
PS
IS
DS
VSS
D8
D9
D10
D11
D12
D13
D14
D15
VSS
D7
D6
D5
D4
D3
D2
D1
D0
SYNC
INT0
INT1
INT2
VCC
DR
FSR
A0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
10
59
11
58
12
57
13
56
14
55
15
54
16
53
17
52
18
51
19
50
20
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
B
C
D
E
F
G
H
J
K
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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V SS
A1
A2
A3
A4
A5
A6
A7
V CC
A8
A9
A10
A11
A12
A13
A14
A15
68-Pin GB Package
(Top View)
1 2 3 4 5 6 7 8 9 10 11
Copyright
2001, Texas Instruments Incorporated
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SMJ320C25, SMJ320C25 50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
description
This data sheet provides design documentation for the SMJ320C25 and the SMJ320C25-50 digital signal
processor (DSP) devices in the SMJ320 family of VLSI digital signal processors and peripherals. The SMJ320
family supports a wide range of digital signal processing applications such as tactical communications,
guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering,
high-speed control, graphics, and other computation-intensive applications.
Differences between the SMJ320C25 and the SMJ320C25-50 are specifically identified, as in the following
paragraph and in the parameter tables on pages 18 through 24 of this data sheet. When not specifically
differentiated, the term SMJ320C25 is used to describe both devices.
The SMJ320C25 has a 100-ns instruction cycle time. The SMJ320C25-50 has an 80-ns instruction cycle time.
With these fast instruction cycle times and their innovative memory configurations, these devices perform
operations necessary for many real-time digital signal processing algorithms. Since most instructions require
only one cycle, the SMJ320C25 is capable of executing 12.5 million instructions per second. On-chip data RAM
of 544 16-bit words, on-chip program ROM of 4K words, direct addressing of up to 64K words of external data
memory space and 64K words of external program memory space, and multiprocessor interface features for
sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the
instruction set.
Table 1. PGA/CLCC/LCCC Pin Assignments
FUNCTION
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
PIN
K1/26
K2/28
L3/29
K3/30
L4/31
K4/32
L5/33
K5/34
K6/36
L7/37
K7/38
L8/39
FUNCTION
A12
A13
A14
A15
BI0
BR
CLKOUT1
CLKOUT2
CLKR
CLKX
D0
D1
PIN
K8/40
L9/41
K9/42
L10/43
B7/68
G11/50
C11/58
D10/57
B9/64
A9/63
F1/18
E2/17
FUNCTION
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
PIN
E1/16
D2/15
D1/14
C2/13
C1/12
B2/11
A2/9
B3/8
A3/7
B4/6
A4/5
85/4
FUNCTION
D14
D15
DR
DS
DX
FSR
FSX
HOLD
HOLDA
IACK
INT0
INT1
PIN
A5/3
B6/2
J1/24
K10/45
E11/54
J2/25
F10/53
A7/67
E10/55
B11/60
G1/20
G2/21
FUNCTION
INT2
IS
MP/MC
MSC
PS
READY
RS
R/W
STRB
SYNC
VCC
VCC
PIN
H1/22
J11/46
A6/1
C10/59
J10/47
B8/66
A8/65
H11/48
H10/49
F2/19
A10/61
B10/62
FUNCTION
VCC
VCC
VSS
VSS
VSS
XF
X1
X2/CLKIN
PIN
H2/23
L6/35
B1/10
K11/44
L2/27
D11/56
G10/51
F11/52
SMJ320 is a trademark of Texas Instruments Incorporated.
2
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SMJ320C25, SMJ320C25 50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Terminal Functions
SIGNALS
VCC
VSS
X1
X2/CLKIN
CLKOUT1
CLKOUT2
D15–D0
A15–A0
PS,DS,IS
R/W
STRB
RS
INT2–INT0
MP/MC
MSC
IACK
READY
BR
XF
HOLD
HOLDA
SYNC
BIO
DR
CLKR
FSR
DX
CLKX
FSX
I/O/Z†
I
I
0
I
0
0
I/O/Z
O/Z
O/Z
O/Z
O/Z
I
I
I
0
0
I
0
0
1
0
I
I
I
I
I
O/Z
I
I/O/Z
5-V supply pins
Ground pins
Output from internal oscillator for crystal
Input to internal oscillator from crystal or external clock
Master clock output (crystal or CLKIN frequency/4)
A second clock output signal
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/0 spaces.
16-bit address bus A15 (MSB) through A0 (LSB)
Program, data, and I/O space select signals
Read / write signal
Strobe signal
Reset input
External user interrupt inputs
Microprocessor/microcomputer mode select pin
Microstate complete signal
Interrupt acknowledge signal
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus
transaction is complete.
Bus request signal. Asserted when the SMJ320C25 requires access to an external global data memory
space.
External flag output (latched software-programmable signal)
Hold input. When asserted, SMJ320C25 goes into an idle mode and places the data, address, and
control lines in the high-impedance state.
Hold acknowledge signal
Synchronization input
Branch control input. Polled by BIOZ instruction
Serial data receive input
Clock for receive input for serial port
Frame synchronization pulse for receive input
Serial data transmit output
Clock for transmit output for serial port
Frame synchronization pulse for transmit. Configurable as either an input or an output.
DEFINITION
† I/O/Z denotes input/output/high-impedance state.
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3
SMJ320C25, SMJ320C25 50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
block diagram
X1
X2/CLKIN
CLKOUT1
CLKOUT2
SYNC
IS
DS
PS
R/W
STRB
READY
BR
XF
HOLD
HOLDA
MSC
BIO
RS
IACK
MP/MC
INT(2-0)
MUX
16
A15-A0
3
16
Program Bus
16
PFC(16)
16
MUX
16
16
16
QIR(16)
IR(16)
STO(16)
ST1(16)
RPTC(8)
IFR(6)
DR
CLKR
FSR
DX
CLKX
FSX
RSR(16)
XSR(16)
Controller
16
16
MCS(16)
16
PC(16)
16
16
Address
Program
ROM/
EPROM
(4096
×
16)
Instruction
16
MUX
16
16
16
16
Stack
(8 x 16)
16
16
16
16
16
16
16
6
8
16
16
DRR(16)
DXR(16)
TIM(16)
PRD(16)
IMR(6)
GREG(8)
D15-D0
Data Bus
16
16
3
AR0(16)
3
ARP(3)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
3
AR5(16)
AR6(16)
AR7(16)
ARB(3)
16
3
ARAU(16)
16
MUX
16
Block B2
(32
×
16)
Data RAM
Block B1
(256
×
16)
16
Data Bus
MUX
16
MUX
16
MUX
16
DATA/PROG
RAM (256
×
16)
Block B0
16
MUX
16
16
32
32
16
9
Shifter(0-16)
DP(9)
16
16
9
7 LSB
From IR
Program Bus
16
TR(16)
16
16
MUX
Multiplier
16
PR(32)
32
Shifter(-6, 0, 1, 4)
32
32
ALU(32)
32
C
ACCH(16)
32
Shifters (0-7)†
16
ACCL(16)
LEGEND:
ACCH =
ACCL =
ALU
=
ARAU =
ARB
=
ARP
=
DP
=
DRR
=
DXR
=
Accumulator high
Accumulator low
Arithmetic logic unit
Auxiliary register arithmetic unit
Auxiliary register pointer buffer
Auxiliary register pointer
Data memory page pointer
Serial port data receive register
Serial port data transmit register
IFR
IMR
IR
MCS
QIR
PR
PRD
TIM
TR
=
=
=
=
=
=
=
=
=
Interrupt flag register
Interrupt mask register
Instruction register
Microcall stack
Queue instruction register
Product register
Period register for timer
Timer
Temporary register
PC
PFC
RPTC
GREG
RSR
XSR
AR0-AR7
ST0, ST1
C
=
=
=
=
=
=
=
=
=
Program counter
Prefetch counter
Repeat instruction counter
Global memory allocation register
Serial port receive shift register
Serial port transmit shift register
Auxiliary registers
Status registers
Carry bit
4
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SMJ320C25, SMJ320C25 50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
architecture
The SMJ320C25 increases performance of DSP algorithms through innovative additions to the SMJ320
architecture. Increased throughput on the SMJ320C25 for many DSP applications is accomplished by means
of single-cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.
The architectural design of the SMJ320C25 emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two contiguous
data blocks, provide increased flexibility in system design. Programs of up to 4K words can be masked into the
internal program ROM. The remainder of the 64K-word program memory space is located externally. Large
programs can execute at full speed from this memory space. Programs can also be downloaded from slow
external memory to high-speed on-chip RAM. A total of 64K data memory address space is included to facilitate
implementation of DSP algorithms. The VLSI implementation of the SMJ320C25 incorporates all of these
features as well as many others, such as a hardware timer, serial port, and block data transfer capabilities.
32-bit ALU/accumulator
The SMJ320C25 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and
logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following
capabilities:
D
Branch to an address specified by the accumulator
D
Normalize fixed-point numbers contained in the accumulator
D
Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other input can be provided from the
product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the
accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
scaling shifter
The SMJ320C25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the
instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or
sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status
register ST1.
16 X 16-bit parallel multiplier
The SMJ320C25 has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned
32-bit product in a single machine cycle. The multiplier has the following two associated registers:
D
A 16-bit temporary register (TR) that holds one of the operands for the multiplier, and
D
A 32-bit product register (PR) that holds the product.
Incorporated into the SMJ320C25 instruction set are single-cycle multiply/accumulate instruction that allow
both operands to be processed simultaneously. The data for these operations can reside anywhere in internal
or external memory and can be transferred to the multiplier each cycle via the program and data buses.
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5
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