P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35 ns (Commercial)
– 15/20/25/35/45 ns (Industrial)
– 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
– 28-Pin 300 mil DIP, SOJ, TSOP
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Plastic and Ceramic DIP
– 28-Pin CERPACK
– 28-Pin Solder Seal Flat Pack
– 28-Pin SOP
– 28-Pin LCC (350 mil x 550 mil)
– 32-Pin LCC (450 mil x 550 mil)
DESCRIPTIOn
The P4C1256 is a 262,144-bit high-speed CMOS static
RAM organized as 32K x 8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1256
is a member of a family of PACE RAM™ products offering
fast access times.
The P4C1256 devices provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
14
. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P4C1256 include 28-pin DIP, SOJ,
and TSOP packages. For military temperature range,
Ceramic DIP and LCC packages are available.
FUnCTIOnAL BLOCK DIAgRAM
PIn COnFIgURATIOnS
DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4, FS-5) SIMILAR
LCC and TSOP configurations at end of datasheet
Document #
SRAM119
REV I
Revised July 2010
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7
-0.5 to VCC + 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
8
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage (TTL
Load)
Output High Voltage (TTL
Load)
Input Leakage Current
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C1256
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
I
OL
= +8 mA, V
CC
= Min
I
OH
= - 4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
P4C1256L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
0.4
2.4
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
0.4
Unit
V
V
V
V
V
V
2.4
-10
-5
-10
-5
—
—
—
—
+10
+5
+10
+5
45
30
20
10
-5
N/A
-5
N/A
—
—
—
—
+5
µA
N/A
+5
µA
N/A
30
mA
N/A
10
mA
N/A
I
LI
I
LO
Output Leakage Current
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
≥ V
IH
, V
CC
= Max, f = Max,
Outputs Open
CE
≥ V
HC
, V
CC
= Max, f = 0,
Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
SB1
Standby Power Supply
Current (CMOS Input
Levels)
N/A = Not applicable
Document #
SRAM119
REV I
Page 2
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
DATA RETEnTIOn CHARACTERISTICS (P4C1256L Military Temperature Only)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
≥ V
CC
-0.2V,
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
0
t
RC§
Test Conditions
Min
2.0
10
15
100
200
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
* T
A
= +25°C
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEnTIOn WAVEFORM
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym
I
CC
Parameter
Dynamic Operating
Current*
Temperature Range
Commercial
Industrial
Military
-12
170
N/A
N/A
-15
160
170
N/A
-20
155
165
170
-25
150
160
165
-35
145
155
160
-45
N/A
150
155
-55
N/A
N/A
150
-70
N/A
N/A
150
Unit
mA
mA
mA
* V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address
Change
Chip Enable to Output in
Low Z
Chip Disable to Output in
High Z
Output Enable Low to
Data Valid
Output Enable Low to
Low Z
Output Enable High to
High Z
Chip Enable to Power Up
Time
Chip Disable to Power
Down Time
0
12
0
5
0
15
2
2
5
5
0
7
0
20
-12
Min
Max
-15
Min
Max
-20
Min
Max
-25
Min
Max
-35
Min
Max
-45
Min
Max
-55
Min
Max
-70
Min
Max
Unit
12
12
12
15
15
15
2
2
8
7
20
20
20
2
2
9
9
0
9
25
25
25
3
3
11
10
0
11
0
20
35
35
35
3
3
15
15
0
15
0
20
45
45
45
3
3
20
20
0
20
0
25
55
55
55
3
3
25
25
0
25
0
30
70
70
70
3
3
30
30
0
30
0
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM119
REV I
Page 3
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
TIMIng WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)
(5)
TIMIng WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)
(5,6)
TIMIng WAVEFORM OF READ CYCLE nO. 3 (CE COnTROLLED)
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM119
REV I
Page 4
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End
of Write
Address Valid to End of
Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in
High Z
Output Active from End of
Write
3
-12
Min
Max
-15
Min
Max
-20
Min
Max
-25
Min
Max
-35
Min
Max
-45
Min
Max
-55
Min
Max
-70
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
12
9
9
0
9
0
8
0
7
15
10
10
0
11
0
9
0
8
3
20
15
15
0
15
0
11
0
10
3
25
18
20
0
18
0
13
0
11
3
35
22
25
0
22
0
15
0
15
3
45
30
35
0
25
0
20
0
18
3
55
35
40
0
30
0
25
0
25
3
70
40
45
0
35
0
30
0
30
3
ns
ns
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(10,11)
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM119
REV I
Page 5
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
