(AV(–40= CDVto +85+3.0 Vf to +5.5 200REF /REF = 2.5 V kHz
External Reference, f
= 4 MHz (for L Version: 1.8 MHz (0 C to +70 C) and MHz
C));
=
kHz (AD7854), 100
DD
DD
IN
OUT
CLKIN
SAMPLE
(AD7854L); T
A
= T
MIN
to T
MAX
, unless otherwise noted.) Specifications in () apply to the AD7854L.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
3
(SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Unipolar Gain Error
Bipolar Positive Full-Scale Error
Negative Full-Scale Error
Bipolar Zero Error
ANALOG INPUT
Input Voltage Ranges
A Version
1
70
B Version
1
71
S Version
1
70
Units
dB min
Test Conditions/Comments
Typically SNR is 72 dB
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz
(L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz
(L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz
(L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz
(L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz
(L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
–78
–78
–78
–78
–78
–78
dB max
dB max
–78
–78
–78
–78
–78
–78
dB typ
dB typ
12
±
1
±
1
±
3
±
2
±
4
±
2
±
4
±
2
±
4
±
2
±
4
0 to V
REF
±
V
REF
/2
±
1
20
2.3/V
DD
150
2.3/2.75
20
3
2.1
0.4
0.6
±
10
10
12
±
0.5
±
1
±
3
±
2
±
4
±
2
±
4
±
2
±
4
±
2
±
4
0 to V
REF
±
V
REF
/2
±
1
20
2.3/V
DD
150
2.3/2.7
20
3
2.1
0.4
0.6
±
10
10
12
±
1
±
1
±
4
±
2
±
4
±
2
±
5
±
2
±
5
±
2
±
5
0 to V
REF
±
V
REF
/2
±
1
20
2.3/V
DD
150
2.3/2.7
20
3
2.1
0.4
0.6
±
10
10
Bits
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
Volts
Volts
5 V Reference V
DD
= 5 V
Guaranteed No Missed Codes to 12 Bits
i.e., AIN(+) – AIN(–) = 0 to V
REF
, AIN(–) can be
biased up but AIN(+) cannot go below AIN(–).
i.e., AIN(+) – AIN(–) = –V
REF
/2 to +V
REF
/2, AIN(–)
should be biased to +V
REF
/2 and AIN(+) can go below
AIN(–) but cannot go below 0 V.
Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
REF
IN
Input Voltage Range
Input Impedance
REF
OUT
Output Voltage
REF
OUT
Tempco
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
µA
max
pF typ
V min/max
kΩ typ
V min/max
ppm/°C typ
V min
V min
V max
V max
µA
max
pF max
Functional from 1.2 V
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
Typically 10 nA, V
IN
= 0 V or V
DD
4
2.4
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
0.4
±
10
10
4
2.4
4
2.4
V min
V min
V max
µA
max
pF max
I
SOURCE
= 200
µA
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
I
SINK
= 0.8 mA
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
Twos Complement
4.6 (9)
0.5 (1)
4.6 (9)
0.5 (1)
Unipolar Input Range
Bipolar Input Range
µs
max
µs
min
t
CLKIN
×
18
(L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
(L Versions Only, –40°C to +85°C, 1 MHz CLKIN)
4.6 (10)
0.5 (1)
–2–
REV. B
AD7854/AD7854L
Parameter
A Version
1
B Version
1
S Version
1
Units
Test Conditions/Comments
POWER REQUIREMENTS
AV
DD,
DV
DD
I
DD
Normal Mode
5
+3.0/+5.5
5.5 (1.8)
5.5 (1.8)
+3.0/+5.5
5.5 (1.8)
5.5 (1.8)
+3.0/+5.5
6 (1.8)
6 (1.8)
V min/max
mA max
mA max
AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA
(1.5 mA);
AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA
(1.5 mA).
Full power-down. Power management bits in control
register set as PMGT1 = 1, PMGT0 = 0.
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1
µA.
Full power-down. Power management
bits in control register set as PMGT1 = 1,
PMGT0 = 0.
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
V
DD
= 5.5 V: Typically 25 mW (8)
V
DD
= 3.6 V: Typically 15 mW (5.4)
V
DD
= 5.5 V
V
DD
= 3.6 V
V
DD
= 5.5 V: Typically 5.5
µW
V
DD
= 3.6 V: Typically 3.6
µW
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
Sleep Mode
6
With External Clock On
10
400
10
400
5
10
400
5
µA
typ
µA
typ
µA
max
µA
typ
mW max
mW max
µW
typ
µW
typ
µW
max
µW
max
V max/min
V max/min
With External Clock Off
5
200
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span
7
Gain Calibration Span
7
30 (10)
20 (6.5)
55
36
27.5
18
200
30 (10)
20 (6.5)
55
36
27.5
18
200
30 (10)
20 (6.5)
55
36
27.5
18
+0.05
×
V
REF
/–0.05
×
V
REF
+0.025
×
V
REF
/–0.025
×
V
REF
NOTES
1
Temperature ranges as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2
Specifications apply after calibration.
3
Not production tested. Guaranteed by characterization at initial product release.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for
CONVST
@ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST
@ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
±
0.025
×
V
REF
(unipolar mode) and V
REF
/2
±
0.025
×
V
REF
(bipolar mode)). This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD7854/AD7854L
TIMING SPECIFICATIONS
Parameter
f
CLKIN2
t
1
t
2
t
CONVERT
t
3
t
4
t
5
t
6
t
7
t
8 4
t
9 5
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
184
t
19
t
20
t
21
t
22
t
23
t
CAL6
t
CAL16
t
CAL26
3
1
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7854 and 1.8 MHz for AD7854L;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit at T
MIN
, T
MAX
(A, B, S Versions)
5V
3V
500
4
1.8
100
50
4.5
10
15
5
0
0
55
50
5
40
60
0
5
0
0
55
10
5
1/2 t
CLKIN
50
50
40
40
2.5 t
CLKIN
31.25
27.78
3.47
500
4
1.8
100
90
4.5
10
15
5
0
0
70
50
5
40
70
0
5
0
0
70
10
5
1/2 t
CLKIN
70
70
60
60
2.5 t
CLKIN
31.25
27.78
3.47
Units
kHz min
MHz max
MHz max
ns min
ns max
µs
max
µs
max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ms typ
ms typ
ms typ
Description
Master Clock Frequency
L Version
CONVST
Pulsewidth
CONVST
to BUSY
↑
Propagation Delay
Conversion Time = 18 t
CLKIN
L Version 1.8 MHz CLKIN. Conversion Time = 18 t
CLKIN
HBEN to
RD
Setup Time
HBEN to
RD
Hold Time
CS
to
RD
to Setup Time
CS
to
RD
Hold Time
RD
Pulsewidth
Data Access Time After
RD
Bus Relinquish Time After
RD
Minimum Time Between Reads
HBEN to
WR
Setup Time
HBEN to
WR
Hold Time
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulsewidth
Data Setup Time Before
WR
Data Hold Time After
WR
New Data Valid Before Falling Edge of BUSY
HBEN High Pulse Duration
HBEN Low Pulse Duration
Propagation Delay from HBEN Rising Edge to Data Valid
Propagation Delay from HBEN Falling Edge to Data Valid
CS↑
to BUSY
↑
in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (125013
t
CLKIN
)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(13889 t
CLKIN
)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The
CONVST
pulsewidth here only applies for normal operation. When the part is in power-down mode, a different
CONVST
pulsewidth applies (see Power-Down
section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
9
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
9
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
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