Preliminary W49L102
64K
×
16 CMOS 3.3V FLASH MEMORY
GENERAL DESCRIPTION
The W49L102 is a 1-megabit, 3.3-volt only CMOS flash memory organized as 64K
×
16 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt V
PP
is
not required. The unique cell architecture of the W49L102 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 3.3-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
•
Single 3.3-volt operations:
−
3.3-volt Read
−
3.3-volt Erase
−
3.3-volt Program
•
Low power consumption
−
Active current: 15 mA (typ.)
−
Standby current: 10
µA
(typ.)
•
•
•
Fast Program operation:
−
Word-by-Word programming: 50
µS
(max.)
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 55/70/90 nS
Endurance: 1K/10K cycles (typ.)
Twenty-year data retention
Hardware data protection
8K word Boot Block with Lockout protection
•
•
•
•
Automatic program and erase timing with
internal V
PP
generation
End of program or erase detection
−
Toggle bit
−
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard word-wide pinouts
Available packages: 40-pin TSOP and 44-pin
PLCC
•
•
•
•
•
•
-1-
Publication Release Date: June 1999
Revision A1
Preliminary W49L102
PIN CONFIGURATIONS
BLOCK DIAGRAM
V
DD
V
SS
A9
A10
A11
A12
A13
A14
A15
NC
WE
V
DD
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
40-pin
TSOP
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
CE
OE
WE
CONTROL
DQ0
OUTPUT
BUFFER
.
.
DQ15
A0
.
.
A15
MAIN
MEMORY
DECODER
(56K Words)
BootBlock
(8K Words)
V
D D D /
Q Q Q C N N D
13 14 15 E C C D
6
5
4
3
2
/
W N
E C
A A
1 1
5 4
1
44 43 42 41 40
39
38
37
36
DQ12
DQ11
DQ10
DQ9
DQ8
GND
NC
DQ7
DQ6
DQ5
DQ4
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
PIN DESCRIPTION
SYMBOL
A0−A15
DQ0−DQ15
CE
OE
WE
V
DD
GND
NC
PIN NAME
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
44-pin
PLCC
35
34
33
32
31
30
29
D D D D
Q Q Q Q
3 2 1 0
/ N A A
O C 0 1
E
A A A
2 3 4
-2-
Preliminary W49L102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49L102 is controlled by CE and OE, both of which have to be low for the
host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is
de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000 hex to 1FFF hex.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block can not be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will only affect the main memory.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the
output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Input Levels
While operating with a 3.0V−3.6V power supply, the address inputs and control inputs (
OE,
CE and
WE ) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to 3.6V.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the main
memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as
before the chip erase operation). The entire memory array (main memory and boot block) will be
erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not
activated. The device will automatically return to normal read mode after the erase operation
completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Main Memory Erase Operation
The main memory erase mode can be initiated by a six-word command sequence. After the
command loading cycle, the device enters the internal main-memory erase mode, which is
automatically timed and will be completed in a fast 100 mS (typical). The host system is not required
-3-
Publication Release Date: June 1999
Revision A1
Preliminary W49L102
to provide any control or timing during this operation. The device will automatically return to normal
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.
Program Operation
The W49L102 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will interally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50
µS
max. -
T
BP
) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49L102 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation is inhibited when V
DD
is less than
1.8V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-
out 10 mS before any write (erase/program) operation.
Data Polling (DQ
7 &
DQ
15
)- Write Status Detection
The W49L102 includes a data polling feature to indicate the end of a program or erase cycle. When
the W49L102 is in the internal program or erase cycle, any attempt to read DQ
7
or DQ
15
of the last
word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
7
or DQ
15
will show the true data. Note that DQ
7
or DQ
15
will show logical "0" during
the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ
6
& DQ
14
)- Write Status Detection
In addition to data polling, the W49L102 provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
or
DQ
14
will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling
between 0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address
0001H outputs the device code (00BFh). The product ID operation can be terminated by a three-word
command sequence or an altenate one-word command sequence (see Command Definition table).
In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.
-4-
Preliminary W49L102
TABLE OF OPERATING MODES
Operating Mode Selection
(V
HH
= 12V
±
0.5V )
MODE
CE
Read
Write
Standby
Write Inhibit
Output Disable
Product ID
V
IL
V
IL
V
IH
X
X
X
V
IL
V
IL
OE
V
IL
V
IH
X
V
IL
X
V
IH
V
IL
V
IL
WE
V
IH
V
IL
X
X
V
IH
X
V
IH
V
IH
A
IN
A
IN
X
X
X
X
PINS
ADDRESS
Dout
Din
High Z
High Z/D
OUT
High Z/D
OUT
High Z
Manufacturer Code
00DA (Hex)
Device Code
00BF (Hex)
DQ.
A0 = V
IL
; A1−A15 = V
IL
;
A9 = V
HH
A0 = V
IH
; A1−A15 = V
IL
;
A9 = V
HH
TABLE OF COMMAND DEFINITION
Command
Description
No. of
Cycles
1st Cycle 2nd Cycle 3rd Cycle
Addr. Data
Addr. Data
Addr. Data
4th Cycle
Addr. Data
5th Cycle
Addr. Data
6th Cycle
Addr. Data
Read
Chip Erase
Main Memory Erase
Word Program
Boot Block Lockout
Product ID Entry
Product ID Exit
(1)
Product ID Exit
(1)
1
6
6
4
6
3
3
1
A
IN
D
OUT
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
5555 80
5555 80
5555 A0
5555 80
5555 90
5555 F0
5555 AA
5555 AA
A
IN
D
IN
2AAA 55
5555 40
2AAA 55
2AAA 55
5555 10
5555 30
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
XXXX F0
5555 AA
Note: Address Format: A14−A0 (Hex); Data Format: DQ15−DQ8 (Don't Care); DQ7-DQ0 (Hex)
Either one of the two Product ID Exit commands can be used.
-5-
Publication Release Date: June 1999
Revision A1
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