IDT70V19L15PFG datasheet, PDF - EEWORLD Datasheet

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IDT70V19L15PFG: DescriptionDual-Port SRAM, 128KX9, 15ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size154KB，17 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70V19L15PFG Overview

Dual-Port SRAM, 128KX9, 15ns, CMOS, PQFP100, TQFP-100

IDT70V19L15PFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	15 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
memory density	1179648 bit
Memory IC Type	DUAL-PORT SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX9
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

IDT70V19L15PFG Preview

HIGH-SPEED 3.3V

128K x 9 DUAL-PORT

STATIC RAM

Features

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

Low-power operation

– IDT70V19L

Active: 440mW (typ.)

Standby: 660µW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT70V19 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

than one device

IDT70V19L

◆

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Functional Block Diagram

R/W

I/O

0-8L

I/O

Control

(1,2)

I/O

Control

I/O

0-8R

(1,2)

BUSY

16L

BUSY

128Kx9

MEMORY

ARRAY

70V19

Address

Decoder

Address

Decoder

16R

R/W

SEM

(2)

INT

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

4853 drw 01

M/S

(1)

NOTES:

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

SEPTEMBER 2003

DSC-4853/4

IDT70V19L

High-Speed 3.3V 128K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT70V19 is a high-speed 128K x 9 Dual-Port Static RAM.

The IDT70V19 is designed to be used as a stand-alone 1152K-bit

Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM

for 18-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-

Port RAM approach in 18-bit or wider memory system applications

results in full-speed, error-free operation without the need for addi-

tional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access

for reads or writes to any location in memory. An automatic power

down feature controlled by the chip enables (either

or CE

)

permit the on-chip circuitry of each port to enter a very low standby

power mode.

Fabricated using IDT’s CMOS high-performance technology,

these devices typically operate on only 440mW of power.

The IDT70V19 is packaged in a 100-pin Thin Quad Flatpack

(TQFP).

Pin Configurations

(1,2,3)

Index

10L

11L

12L

13L

14L

15L

16L

Vcc

SEM

R/W

GND

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

INT

BUSY

GND

M/S

BUSY

INT

IDT70V19PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

10R

11R

12R

13R

14R

15R

16R

GND

SEM

R/W

GND

4853 drw 02

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

GND

I/O

GND

I/O1

I/O

Vcc

GND

I/O

Vcc

I/O

IDT70V19L

High-Speed 3.3V 128K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

, CE

R/W

- A

16L

I/O

- I/O

SEM

INT

BUSY

Right Port

, CE

R/W

- A

16R

I/O

- I/O

SEM

INT

BUSY

M/S

GND

Names

Chip Enables

Read/Write Enable

Output Enable

Address

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

Master or Slave Select

Power

Ground

4853 tbl 01

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage

with Respect

to GND

Temperature

Under Bias

Storage

Temperature

DC Output

Current

Commercial

& Industrial

-0.5 to +4.6

Unit

Recommended DC Operating

Conditions

Symbol

GND

Parameter

Supply Voltage

Ground

Input High Voltage

Input Low Voltage

Min.

3.0

2.0

-0.3

(1)

Typ.

3.3

____

Max.

3.6

+0.3

(2)

0.8

Unit

4853 tbl 04

BIAS

STG

OUT

-55 to +125

-65 to +150

____

4853 tbl 02

NOTES:

1. V

> -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 0.3V.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> Vcc + 0.3V.

Capacitance

(1)

Symbol

OUT

Parameter

Input Capacitance

= +25°C, f = 1.0MHz)

Conditions

(2)

= 3dV

OUT

= 3dV

Max.

Unit

4853 tbl 05

Output Capacitance

Maximum Operating Temperature

and Supply Voltage

Grade

Commercial

Industrial

Ambient

Temperature

(1)

C to +70

-40

C to +85

GND

Vcc

3.3V

0.3V

3.3V

0.3V

4853 tbl 03

NOTES:

1. This parameter is determined by device characterization but is not produc-

tion tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

NOTE:

1. This is the parameter T

. This is the "instant on" case temperature.

IDT70V19L

High-Speed 3.3V 128K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I – Chip Enable

(1,2)

< 0.2V

-0.2V

(3)

Mode

Port Selected (TTL Active)

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

Port Deselected (CMOS Inactive)

4853 tbl 06

-0.2V

(3)

<0.2V

NOTES:

1. Chip Enable references are shown above with the actual

and CE

levels;

is a reference only.

2. 'H' = V

and 'L' = V

3. CMOS standby requires 'X' to be either < 0.2V or >V

-0.2V.

Truth Table II – Non-Contention Read/Write Control

Inputs

(1)

(2)

R/W

SEM

Outputs

I/O

0-8

High-Z

DATA

OUT

High-Z

Deselected: Power-Down

Write to Memory

Read Memory

Outputs Disabled

4853 tbl 07

Mode

NOTES:

1. A

— A

16L

≠

— A

16R

2. Refer to Truth Table I - Chip Enable.

Truth Table III – Semaphore Read/Write Control

(1)

Inputs

(2)

R/W

↑

SEM

Outputs

I/O

0-8

DATA

OUT

DATA

______

Mode

Read Semaphore Flag Data Out

Write I/O

into Semaphore Flag

Not Allowed

4853 tbl 08

NOTES:

1. There are eight semaphore flags written to I/O

and read from all the I/Os (I/O

-I/O

). These eight semaphore flags are addressed by A

-A

2. Refer to Truth Table I -

Chip Enable

IDT70V19L

High-Speed 3.3V 128K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V ± 0.3V)

70V19L

Symbol

Parameter

Input Leakage Current

(1)

Output Leakage Current

Output Low Voltage

Output High Voltage

Test Conditions

= 3.6V, V

= 0V to V

(2)

= V

, V

OUT

= 0V to V

= +4mA

= -4mA

Min.

___

Max.

0.4

___

Unit

µA

4853 tbl 09

___

2.4

NOTES:

1. At Vcc

2.0V, input leakages are undefined.

2. Refer to Truth Table I -

Chip Enable.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(5)

= 3.3V ± 0.3V)

70V19L15

Com'l Only

Symbol

Parameter

Dynamic Operating

Current

(Both Ports Active)

Standby Current

(Both Ports - TTL Level

Inputs)

Standby Current

(One Port - TTL Level

Inputs)

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Full Standby Current

(One Port - All CMOS

Level Inputs)

Test Condition

= V

, Outputs Disabled

SEM

= V

f = f

MAX

(2)

= V

SEM

= V

f = f

MAX

(2)

"A"

= V

and

"B"

= V

(4)

Active Port Outputs Disabled,

f=f

MAX

(2)

SEM

= V

Both Ports

and

> V

- 0.2V,

> V

- 0.2V or V

< 0.2V, f = 0

(3)

SEM

> V

- 0.2V

"A"

< 0.2V and

"B"

> V

- 0.2V

(4)

SEM

> V

- 0.2V,

> V

- 0.2V or V

< 0.2V,

Active Port Outp uts Disabled , f = f

MAX

(2)

Version

COM'L

IND

COM'L

IND

COM'L

IND

COM'L

IND

COM'L

IND

Typ.

(1)

145

---

100

---

0.2

---

Max.

235

---

155

---

3.0

---

150

---

70V19L20

Com'l

& Ind

Typ.

(1)

135

0.2

Max.

205

220

140

150

3.0

135

145

4853 tbl 10

Unit

SB1

SB2

SB3

SB4

NOTES:

1. V

= 3.3V, T

= +25°C, and are not production tested. I

CCDC

= 90mA (Typ.)

2. At f = f

MAX

address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t

RC,

and using “AC Test Conditions" of input levels of GND

to 3V.

3. f = 0 means no address or control lines change.

4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

5. Refer to Truth Table I - Chip Enable.

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IDT70V19L15PFG Related Products

	IDT70V19L15PFG	IDT70V19L20PFG	IDT70V19L20PFGI	IDT70V19L15PF9	IDT70V19L20PF9
Description	Dual-Port SRAM, 128KX9, 15ns, CMOS, PQFP100, TQFP-100	Dual-Port SRAM, 128KX9, 20ns, CMOS, PQFP100, TQFP-100	Dual-Port SRAM, 128KX9, 20ns, CMOS, PQFP100, TQFP-100	Dual-Port SRAM, 128KX9, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 128KX9, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Is it lead-free?	Lead free	Lead free	Lead free	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP	QFP
package instruction	TQFP-100	TQFP-100	TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts	100	100	100	100	100
Reach Compliance Code	compliant	compliant	compliant	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	15 ns	20 ns	20 ns	15 ns	20 ns
JESD-30 code	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e3	e3	e3	e0	e0
length	14 mm	14 mm	14 mm	14 mm	14 mm
memory density	1179648 bit	1179648 bit	1179648 bit	1179648 bit	1179648 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	9	9	9	9	9
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	100	100
word count	131072 words	131072 words	131072 words	131072 words	131072 words
character code	128000	128000	128000	128000	128000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C	70 °C	70 °C
organize	128KX9	128KX9	128KX9	128KX9	128KX9
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	240	240
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	MATTE TIN	MATTE TIN	MATTE TIN	TIN LEAD	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	20	20
width	14 mm	14 mm	14 mm	14 mm	14 mm

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