W2465A
8K
×
8 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W2465A is a high-speed, low-power CMOS static RAM organized as 8192
×
8 bits that operates
on a single 5-volt power supply. This device is manufactured using Winbond's high performance
CMOS technology.
FEATURES
•
•
High-speed access time: 12/15/20 nS (max.)
Low-power consumption:
−
Active: 400mW (typ.)
Single +5V power supply
Fully static operation
•
•
•
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 28-pin 300 mil SOJ and
skinny DIP
•
•
PIN CONFIGURATION
BLOCK DIAGRAM
V
DD
V
SS
A0
.
.
A12
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
WE
CS2
DECODER
CORE
C O RE
ARRAY
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
CS1
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
PIN DESCRIPTION
SYMBOL
A0−A12
I/O1−I/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
-1-
Publication Release Date: October 1995
Revision A6
W2465A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +7.0
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to +70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
TRUTH TABLE
CS1
H
X
L
L
L
CS2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
MODE
Not Selected
Not Selected
Output Disable
Read
Write
I/O1−I/O8
High Z
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
DD
I
DD
I
DD
OPERATING CHARACTERISTICS
(V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= 0 to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
SYM.
V
IL
V
IH
I
LI
I
LO
TEST CONDITIONS
-
-
V
IN
= V
SS
to V
DD
V
I/O
= V
SS
to V
DD,
CS1 = V
IH
or CS2 = V
IL
or
OE
= V
IH
or
WE
= V
IL
I
OL
= +8.0 mA
I
OH
= -4.0 mA
12
CS1 = V
IL
CS2 = V
IH
I/O = 0 mA
Cycle = MIN
Duty = 100%
15
20
MIN.
-0.5
+2.2
-10
-10
TYP.
-
-
-
-
MAX.
+0.8
V
DD
+0.5
+10
+10
UNIT
V
V
µA
µA
V
OL
V
OH
I
DD
-
2.4
-
-
-
-
-
-
-
-
-
-
0.4
-
180
150
120
30
V
V
mA
mA
mA
mA
Standby Power
Supply Current
I
SB
CS1= V
IH
or CS2 = V
IL
Cycle = MIN
Duty = 100%
CS1
≥
V
DD
-0.2V
or CS2
≤
0.2V
I
SB1
-
-
5
mA
Note: Typical characteristics are at V
DD
= 5V, T
A
= 25° C.
-2-
W2465A
CAPACITANCE
(V
DD
= 5V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
8
10
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3V
5 nS
1.5V
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
CONDITIONS
AC TEST LOADS AND WAVEFORM
R1 480 ohm
R1 480 ohm
5V
OUTPUT
30 pF
Including
Jig and
Scope
R2
255 ohm
5V
OUTPUT
5 pF
Including
Jig and
Scope
R2
255 ohm
(For T
CLZ1,
T
CLZ2,
T
OLZ,
T
CHZ1,
T
CHZ2,
T
OHZ,
T
WHZ,
T
OW
)
3.0V
90%
10%
5 nS
10%
90%
0V
5 nS
-3-
Publication Release Date: October 1995
Revision A6
W2465A
AC CHARACTERISTICS
(V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= 0 to 70° C)
Read Cycle
PARAMETER
SYM.
W2465A-12
MIN.
Read Cycle Time
Address Access Time
Chip Select
Access Time
Output Enable to Output Valid
Chip Selection to
Output in Low Z
CS1
CS1
W2465A-15
MIN.
15
-
-
-
-
3
3
0
-
-
-
3
MAX.
-
15
15
15
7
-
-
-
7
7
7
-
W2465A-20
MIN.
20
-
-
-
-
3
3
0
-
-
-
3
MAX.
-
20
20
20
10
-
-
-
10
10
10
-
UNIT
MAX.
-
12
12
12
6
-
-
-
6
6
6
-
T
RC
T
AA
T
ACS1
T
ACS2
T
AOE
T
CLZ1
*
T
CLZ2
*
T
OLZ
*
T
CHZ1
*
T
CHZ2
*
T
OHZ
*
T
OH
12
-
-
-
-
3
3
0
-
-
-
3
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
CS2
CS2
Output Enable to Output in Low Z
Chip Deselection
to Output in High Z
CS1
CS2
Output Disable to Output in High Z
Output Hold from Address Change
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W2465A-12
MIN.
Write Cycle Time
Chip Selection to
End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
CS1
,
WE
CS1
W2465A-15
MIN.
15
13
13
13
0
10
0
0
9
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
-
-
8
8
-
W2465A-20
MIN.
20
17
17
17
0
12
0
0
10
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
-
-
10
10
-
UNIT
MAX.
-
-
-
-
-
-
-
-
-
-
7
7
-
T
WC
T
CW1
T
CW2
T
AW
T
AS
T
WP
T
WR1
T
WR2
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
12
10
10
10
0
10
0
0
7
0
-
-
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
CS2
CS2
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
* These parameters are sampled but not 100% tested.
-4-
W2465A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
OH
D
OUT
T
AA
T
OH
Read Cycle 2
(Chip Select Controlled)
CS1
T
ACS1
T
CHZ1
CS2
T
ACS2
T
CHZ2
T
CLZ1
D
OUT
T
CLZ2
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
T
OH
CS1
T
OLZ
T
ACS1
T
CLZ1
T
CHZ1
CS2
T
ACS2
T
CLZ2
T
CHZ2
T
OHZ
D
OUT
-5-
Publication Release Date: October 1995
Revision A6
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