Features
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Utilizes the AVR
®
RISC Architecture
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AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Nonvolatile Program Memory
– 8K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes of SRAM
– 512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler
Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down Mode: <1 µA
I/O and Packages
– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC and TQFP
Operating Voltages
– 2.7 - 6.0V (AT90S8515-4)
– 4.0 - 6.0V (AT90S8515-8)
Speed Grades
– 0 - 4 MHz (AT90S8515-4)
– 0 - 8 MHz (AT90S8515-8)
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•
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•
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8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8515
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Pin Configurations
Rev. 0841F–12/00
1
Description
The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful
instructions in a single clock cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz, allowing the sys-
tem designer to optimize power consumption versus processing speed.
Block Diagram
Figure 1.
The AT90S8515 Block Diagram
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AT90S8515
AT90S8515
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The AT90S8515 provides the following features: 8K bytes of In-System Programmable Flash, 512 bytes EEPROM, 512
bytes SRAM, 32 general-purpose I/O lines, 32 general-purpose working registers, flexible timer/counters with compare
modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscilla-
tor, an SPI serial port and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the
SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down Mode saves the register
contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip In-System Program-
mable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a
conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable
Flash on a monolithic chip, the Atmel AT90S8515 is a powerful microcontroller that provides a highly flexible and cost-
effective solution to many embedded control applications.
The AT90S8515 AVR is supported with a full suite of program and system development tools including: C compilers, macro
assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions
VCC
Supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A
output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are
externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port A serves as multiplexed address/data input/output when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S8515 as listed on page 57.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port C also serves as address output when using external SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S8515 as listed on page 63.
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RESET
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses
are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
ICP
ICP is the input pin for the Timer/Counter1 Input Capture function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output CompareB function.
ALE
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the first access cycle, and the AD0 - 7 pins are used for data during
the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip
oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2.
Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
XTAL2
XTAL1
GND
Note:
When using the MCU oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
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AT90S8515
AT90S8515
Figure 3.
External Clock Drive Configuration
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed and the result is stored back in the register file – in one clock
cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look-up function. These added function registers are the 16-bit X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the AT90S8515 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters,
A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program
memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 4K address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 16-bit Stack Pointer (SP) is read/write-accessible in the I/O space.
The 512-byte data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
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Analog electronics
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