UPD65948S1-068 datasheet, PDF - EEWORLD Datasheet

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UPD65948S1-068: DescriptionMultifunction Peripheral, CMOS, PBGA256, TBGA-256; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1003KB，160 Pages; ManufacturerNEC Electronics

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UPD65948S1-068 Overview

Multifunction Peripheral, CMOS, PBGA256, TBGA-256

UPD65948S1-068 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	BGA
package instruction	LBGA,
Contacts	256
Reach Compliance Code	compliant
Address bus width	32
boundary scan	NO
Bus compatibility	VR43XX
maximum clock frequency	66 MHz
External data bus width	32
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	27 mm
Number of terminals	256
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27 mm

UPD65948S1-068 Preview

4375 System Controller

Data Sheet

August 2000

Description

The V

4375

system controller is a software-configurable chip that interfaces directly

with an NEC V

43xx

64-bit MIPS



RISC CPU and PCI bus without external logic or

buffering. The system controller also interfaces with memory (SDRAM, EDO, fast-page

DRAM, and flash/boot ROM) with minimal to no buffering. The memory bus can also

interface with SRAM and general-purpose I/O devices. As an interface with the V

43xx

CPU, the V

4375 acts as a memory controller, DMA controller, and PCI bridge. As an

interface with PCI agents, the V

4375 acts as either a PCI bus master or a PCI bus

target. Alternatively, the V

4375 may be located on a PCI bus add-on board.

Features

CPU Interface

•

Direct connection to the 66 MHz V

43xx CPU bus

3.3-volt I/O

Support for all V

43xx bus cycles

Little-endian or big-endian byte ordering modes

Support for boot ROM/flash memory, base memory, and up to two SIMMs

SIMM capacity of up to 128 MB

Programmable address ranges for base and SIMM memory

Support for two-bank 4/16 Mb devices and four-bank 64/128/256 Mb devices

CAS latency of 2 or 3 in base memory or SIMM SDRAM, programmable to

support faster new devices or slower legacy devices

SIMM burst access time programmable in one or two cycle(s)

66 MHz memory bus

64 MB base memory range: SDRAM and EDO DRAM

256 MB SIMM memory range: SDRAM, EDO and fast-page DRAM

Several speed grades supported within each memory range

Open DRAM page maintained within base memory

Eight-word (32-byte) write FIFO (CPU to memory)

Two-word (8-byte) prefetch FIFO (memory to CPU or memory to PCI)

On-chip DRAM and SDRAM refresh generation

Up to 64 MB of write-protectable boot ROM or up to 64 MB of flash ROM

Flash/boot ROM devices with 8-/16-/32-bit configuration support

Programmable timing to interface general-purpose I/O device or boot ROM in

the boot ROM address range

Memory Interface

•

U13749EU2V0DS00

NEC VRC chipsets are designed and Verified for use with NEC VR Series™ microprocessors. NEC makes

no claim as to the suitability of VRC chipsets for use with non-NEC microprocessors and does not warrant

their performance, suitability or use in such applications.

4375 System Controller

PCI Interface

•

Master and target capabilities

Host bridge and add-on board modes

PCI bus arbiter with programmable arbitration scheme

Programmable arbitration scheme for PCI/CPU accessed to memory

Big-endian or little-endian byte ordering modes

4-word (16-byte) bidirectional PCI master FIFO (CPU is PCI bus master)

8-word (32-byte) bidirectional PCI target FIFO (memory is PCI bus target)

33 MHz PCI bus clock rate

132 MB/s burst transfers

Interrupt support for add-on board mode

3.3 V inputs; 5 V-tolerant inputs/outputs

Four highly robust DMA channels

CPU-initiated block transfers between memory and PCI bus

8-word (32-byte) bidirectional DMA FIFO

Sophisticated, programmable DMA channel arbitration priority scheme

Four sets of DMA control registers for chained transfers

Next address pointer in each channel to support scatter/gather operation

Programmable DMA arbitration priority

Bidirectional unaligned transfers

Transfers at maximum PCI bandwidth of 132 MB/s

Nonmaskable interrupt and interrupt signals (NMI# and INT#)

Maskable interrupt-causing events

NY16550L Universal Asynchronous Receiver/Transmitter

Modem control functions

Separate receiver and transmitter FIFOs (16 bytes each)

Even-, odd- or no-parity bit generation

Fully prioritized interrupt control

One 32-bit loadable watchdog timer that generates a nonmaskable interrupt

Two 32-bit loadable general-purpose timers that generate interrupts

Highly sophisticated timers with programmable clock, start/stop, auto reload/

restart, and enable/disable interrupt bits

DMA Controller

•

Interrupt Controller

•

UART

Timers

•

Ordering

Information

Part Number

4375

µPD65948S1-068

Package

256-pin TBGA

4375 System Controller

System

Configuration

Figure 1 shows the controller used as a host bridge in a typical system. Alternatively,

the controller can be located on a PCI bus Add-On Board.

Figure 1. System Connection

Memory

32 bits, 66 MHz

4375

43xx

CPU

32 bits, 66 MHz

System

Controller

PCI Bus

32 bits, 33 MHz

UART

Note:

F244- or F245-type buffers may be needed on the MuxAD bus and, for DIMM, on certain chip-select

signals.

4375 System Controller

Terminology

In this document:

Reference

Documents

Signal names ending with # (such as NMI#)

are active-low signals.

Word

means 4 bytes. This definition of word differs from the definition in the

PCI

Local Bus Specification,

where a word is 2 bytes.

means byte.

means bit.

CAS

means column address strobe.

Memory

means the local memory attached to the V

4375 controller.

SIMM

and

DIMM

mean single and dual in-line memory module unless

explicitly stated otherwise.

Module

means a set of chips, as in a SIMM or DIMM.

EDO DRAM

means extended data out dynamic random access memory.

SDRAM

means synchronous DRAM.

RDRAM



means Rambus



DRAM, which is designed to conform to the interface

that defines the Rambus Channel.

The following documents were used in the creation of this data sheet. Unless other-

wise specified, the latest version of each document applies.

MIPS

R4300 Preliminary RISC Processor Specification Revision 2.2

(available

from MIPS Technologies, Inc.)

PCI Local Bus Specification Revision 2.1

and

PCI System Design Guide Revision

1.0

(available from the Peripheral Component Interconnect Special Interest

Group)

NEC

4300

Microprocessor User’s Manual

(document number

U10504EJ6V0UM00)

4375 System Controller

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

13.0

14.0

15.0

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Registers, Resources, and Implementation . . . . . . . . . . . . . . . . . . . 14

CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Reset Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Endian Mode Software Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

UPD65948S1-068 Related Products

	UPD65948S1-068
Description	Multifunction Peripheral, CMOS, PBGA256, TBGA-256
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	BGA
package instruction	LBGA,
Contacts	256
Reach Compliance Code	compliant
Address bus width	32
boundary scan	NO
Bus compatibility	VR43XX
maximum clock frequency	66 MHz
External data bus width	32
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	27 mm
Number of terminals	256
Maximum operating temperature	70 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27 mm

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