CD4066BF datasheet, PDF - EEWORLD Datasheet

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CD4066BF: DescriptionCD4066BF; CategoryAnalog mixed-signal IC The signal circuit; File Size276KB，5 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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CD4066BF Overview

CD4066BF

CD4066BF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	not_compliant
Analog Integrated Circuits - Other Types	SPST
JESD-30 code	R-CDIP-T14
JESD-609 code	e0
normal position	NO
Number of functions	4
Number of terminals	14
Maximum on-state resistance (Ron)	1300 Ω
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
output	SEPARATE OUTPUT
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
Certification status	Not Qualified
Maximum seat height	5.08 mm
surface mount	NO
Maximum connection time	70 ns
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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CD4066B Types

COS/MOS Quad Bilateral

Switch

For Transmission or Multiplexing of Analog or

Digital Signals

Features:

High-Voltage Types (20-Volt Rating)

The RCA-CD40668 IS a quad bilateral SWitch

Intended for the transmission or multiplex-

Ing of analog or digl tal Signals. It is pin-for·

pin compatible with RCA-CD40168, but

exhibits a much lower on-state resistance. In

addition, the on-state resistance IS relatively

constant over the full input-signal range.

The CD40668 consists of four independent

bilateral SWitches. A Single control Signal is

required per SWitch. 80th the p and the n

deVice in a given switch are biased on or

off simultaneously

by the control signal.

As shown in Fig_ 1, the well of the n-channel

deVice on each SWitch IS either tied to the

input when the switch is on or to VSS when

the switch IS off. This configuration elimi-

nates the variation of the SWitch-tranSistor

threshold voltage with input signal, and thus

keeps the on-state resistance low over the full

operating-signal range.

The advantages over Single-channel switches

include peak input-signal voltage swings equal

to the full supply Voltage, and more constant

on-state Impedance over the input-signal

range_ For sample-and-hold applications,

however, the CD40168 IS recommended.

The C04066B is available In 14-lead ceramic

dual-in-line packages (0 and F suffixes).

14-lead plastic dual-in-line packages (E suf-

fix). 14-lead ceramic flat pac;kages (K suffix).

and In chip form (H suffix).

•

15-V digital or ±7.5-V peak-to-peak switching

• 125n typical on-state resistance for 15-V operation

• Switch on-state resistance matched to within 5 n over

15-V signal-input range

• On-state resistance flat over full peak-to-peak signal

range

• High on/off output-voltage ratio: 80 dB typo

fis

10 kHz. R L

1 kn

• High degree of linearity: <0.5% distortion

FUNCTIONAL DIAGRAM

typo

fis

1 kHz, Vis

5 VP-P. VOO -

VSS

10 V, RL

10 kn

• Extremely lOw off-state swtch leakage

resulting in very low

offset

current and high

effective off-state resistance: 10 pA typo

Applications:

VOO - VSS

10 V, TA

• Analog signal switching/multiplexing

Signal gating

Modulator

• Extremely high control input impedan.;e

Squelch control

Demodulator

(control circuit isolated from signal cir-

Chopper

Commutating switch

cuit): 10 12 n typo

• Digital signal switching/Multiplexing

• Low crosstalk between switches: -50 dB

typo

fis

8 MHz, RL

1 kn

• Transmission-gate logic implementation

• Matched control-input to signal-output

• Analog-to-digital

digital-to-analog

capacitance: Reduces output signal

conversion

transients

• Digital control of frequency, impedance,

• Frequency response, switch on

40 MHz

phase, and analog-signal gain

(typ.)

• 100% tested for quiescent current at 20 V

• 5-V, 10-V, and 15-V parametric ratings

• Meets all requirements of JEOEC Tentative

Standard No.13A, "Standard Specifications

for Description of "B" Series CMOS Devices"

MAXIMUM

RATINGS,

Absolute-MaxImum Values

DC SUPPL Y-VOL TAGE RANGE. (VDD'

(Voltages referl!nced to VSS Termlnall

-05 to +20 V

INPUT VOLTAGE RANGE. ALL INPUTS

-05 to V DD +05 V

DC INPUT CURRENT. ANY ONE INPUT (except for

TRANSMIS~I.)N

GATE which IS 25 mAl

±10 mA

POWER DISSIPATION PoER PACKAGE (PO'

For T A : -40 to +60 C IPACKAGE TYPE E)

500mW

Derate Lln"_ '., at 12 mWI C to 200 mW

For T A : +60 to +85

(PACKAGE TYPE E)

(PACKAGE TYPES D. F)

For T A

-55 to +100

500mW

For T A: +100 to +125 C (PACKAGE TYPES D. F)

Derate Linearly at 12 mWI C to 200 mW

DEVICE DISSIPATION PER OUTPUT TRANSISTOR

FOR TA

FULL PACKAGE-TEMPERATURE RANGE (All Package Types)

100mW

OPERATING-TEMPERATURE RANGE (T A)

PACKAGE TYPES 0, F. H

-55 to +125°C

PACKAGE TYPE E

-40 to +85:C

STORAGE TEMPERATURE RANGE (T

-65 to +150 C

LEAD TEMPERATURE lOURING

SOLD~RINGI

At distance 1/16 ±

1/32

Inch 1159 ± 079 mml from case for 10 s max

NORMAL OPERATION

CONTROL-LINE BIASING

SWITCH ON.Vc"-·VDO

SWITCH OFF, VC -0' 'VSS

~~~E·p'SUBSTRATES

CONNECTED TO VDD

----

'*ALL CONTROL INPUTS ARE

PROTECTEO BY

COSI

MOS

PROTECTION NETWORK

Vss

RECOMMENDED OPERATING CONDITIONS

For maximum reliability, nominal operating conditions should be selected so that oper-

ation is always within the following ranges:

CHARACTERISTIC

Supply-Voltage Range (For T A

Full Package-

Temperature Range)

LIMITS

Min.

Max.

UNITS

FIg.

1 -

SchematIC dIagram of

identical

SWItches and its associated control

C/fCUltry.

218 ____________________________________________________________________________

CD4066BF Related Products

	CD4066BF	CD4066BE	CD4066BK	CD4066BH	CD4066BD
Description	CD4066BF	SGL POLE SGL THROW SWITCH, PDIP14, PLASTIC, DIP-14	CD4066BK	SGL POLE SGL THROW SWITCH, UUC, DIE	CD4066BD
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	DIP	DIP	DIP	DIE	DIP
package instruction	DIP, DIP14,.3	DIP, DIP14,.3	CERAMIC, DIP-14	,	HERMET SEALED, CERAMIC, DIP-14
Reach Compliance Code	not_compliant	not_compliant	not_compliant	unknown	not_compliant
Analog Integrated Circuits - Other Types	SPST	SPST	SPST	SPST	SPST
JESD-30 code	R-CDIP-T14	R-PDIP-T14	R-XDFP-F14	R-XUUC-N	R-CDIP-T14
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	FLATPACK	UNCASED CHIP	IN-LINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	NO	NO	YES	YES	NO
Terminal form	THROUGH-HOLE	THROUGH-HOLE	FLAT	NO LEAD	THROUGH-HOLE
Terminal location	DUAL	DUAL	DUAL	UPPER	DUAL
Is it Rohs certified?	incompatible	incompatible	incompatible	-	incompatible
Contacts	14	14	14	-	14
JESD-609 code	e0	e0	e0	-	e0
normal position	NO	NO	NO	-	NO
Number of functions	4	4	4	-	4
Number of terminals	14	14	14	-	14
Maximum on-state resistance (Ron)	1300 Ω	1200 Ω	1300 Ω	-	1300 Ω
Maximum operating temperature	125 °C	85 °C	125 °C	-	125 °C
Minimum operating temperature	-55 °C	-40 °C	-55 °C	-	-55 °C
output	SEPARATE OUTPUT	SEPARATE OUTPUT	SEPARATE OUTPUT	-	SEPARATE OUTPUT
encapsulated code	DIP	DIP	DFP	-	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	FL14,.3	-	DIP14,.3
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED
power supply	5/15 V	5/15 V	5/15 V	-	5/15 V
Maximum seat height	5.08 mm	5.33 mm	-	-	5.08 mm
Maximum connection time	70 ns	70 ns	70 ns	-	70 ns
technology	CMOS	CMOS	CMOS	-	CMOS
Temperature level	MILITARY	INDUSTRIAL	MILITARY	-	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal pitch	2.54 mm	2.54 mm	1.27 mm	-	2.54 mm
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED
width	7.62 mm	7.62 mm	-	-	7.62 mm

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