FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver
September 2008
FAN3121 / FAN3122
Single 9A High-Speed, Low-Side Gate Driver
Features
Industry-Standard Pin-out with Enable Input
4.5 to 18V Operating Range
11.4A Peak Sink at V
DD
= 12V
9.7A Sink / 7.1A Source at V
OUT
= 6V
Inverting Configuration (FAN3121) and
Non-Inverting Configuration (FAN3122)
Internal Resistors Turn Driver Off If No Inputs
23ns/19ns Typical Rise/Fall Times with 10nF Load
20ns Typical Propagation Delay Time
Choice of TTL or CMOS Input Thresholds
MillerDrive™ Technology
Available in Thermally Enhanced 3x3mm 8-Lead
MLP or 8-Lead SOIC Package (Pb-Free Finish)
Rated from –40°C to +125°C
Description
The FAN3121 and FAN3122 MOSFET drivers are
designed to drive N-channel enhancement MOSFETs in
low-side switching applications by providing high peak
current pulses. The drivers are available with either TTL
(FAN312xT) or CMOS (FAN312xC) input thresholds.
Internal circuitry provides an under-voltage lockout
function by holding the output low until the supply
voltage is within the operating range.
FAN312x drivers incorporate the MillerDrive™
architecture for the final output stage. This bipolar /
MOSFET combination provides the highest peak
current during the Miller plateau stage of the MOSFET
turn-on / turn-off process.
The FAN3121 and FAN3122 drivers implement an
enable function on pin 3 (EN), previously unused in the
industry-standard pin-out. The pin is internally pulled up
to V
DD
for active HIGH logic and can be left open for
standard operation.
The FAN3121/22 is available in a 3x3mm 8-lead thermally-
enhanced MLP package or an 8-lead SOIC package.
Applications
Synchronous Rectifier Circuits
High-Efficiency MOSFET Switching
Switch-Mode Power Supplies
DC-to-DC Converters
Motor Control
VDD 1
IN
EN
2
3
8
7
6
5
VDD
OUT
OUT
GND
VDD 1
IN
EN
2
3
8 VDD
7 OUT
6 OUT
5 GND
GND 4
GND 4
Figure 1.
FAN3121 Pin Configuration
Figure 2.
FAN3122 Pin Configuration
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
www.fairchildsemi.com
FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver
Ordering Information
Part Number
FAN3121CMPX
FAN3121CMX
FAN3121TMX
FAN3122CMPX
FAN3122CMX
FAN3122TMX
Non-Inverting Channels +
FAN3122TMPX Enable
Inverting Channels +
FAN3121TMPX Enable
Logic
Input
Threshold
CMOS
TTL
CMOS
TTL
Package
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
Eco
Status
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
Packing
Method
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Quantity
per Reel
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
Package Outlines
Figure 3.
3x3mm MLP-8 (Top View)
Figure 4.
SOIC-8 (Top View)
Thermal Characteristics
(1)
Package
8-Lead 3x3mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Θ
JL
(2)
Θ
JT
(3)
Θ
JA
(4)
Ψ
JB
(5)
Ψ
JT
(6)
Units
°C/W
°C/W
1.2
38
64
29
42
87
2.8
41
0.7
2.3
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (Θ
JL
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
3. Theta_JT (Θ
JT
): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
4. Theta_JA (Θ
JA
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards
JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Psi_JB (Ψ
JB
): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 4. For
the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and
protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB
copper adjacent to pin 6.
6. Psi_JT (Ψ
JT
): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 4.
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
www.fairchildsemi.com
2
FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver
VDD 1
IN
EN
2
3
8
7
6
5
VDD
OUT
OUT
GND
VDD 1
IN
EN
2
3
8 VDD
7 OUT
6 OUT
5 GND
GND 4
GND 4
Figure 5.
FAN3121 Pin Assignments (Repeated)
Figure 6.
FAN3122 Pin Assignments (Repeated)
Pin Definitions
FAN3121
3
4, 5
2
FAN3122
3
4, 5
2
6, 7
Name
EN
GND
IN
OUT
OUT
Description
Enable Input.
Pull pin LOW to inhibit driver. EN has logic thresholds for both
TTL and CMOS IN thresholds.
Ground.
Common ground reference for input and output circuits.
Input.
Gate Drive Output.
Held LOW unless required input is present and V
DD
is
above the UVLO threshold.
Gate Drive Output
(inverted from the input). Held LOW unless required input
is present and V
DD
is above the UVLO threshold.
Supply Voltage.
Provides power to the IC.
Thermal Pad (MLP only).
Exposed metal on the bottom of the package; may
be left floating or connected to GND; NOT suitable for carrying current.
6, 7
1, 8
1, 8
V
DD
P1
Output Logic
FAN3121
EN
0
0
1
1
(7)
(7)
FAN3122
OUT
0
0
1
0
EN
0
0
1
1
(7)
(7)
IN
0
1
1
(7)
IN
0
0
(7)
OUT
0
0
0
1
1
(7)
0
(7)
1
Note:
7. Default input signal if no external connection is made.
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
www.fairchildsemi.com
3
FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver
Block Diagram
V
DD
1
100k
8
V
DD
Inverting
(FAN3121)
UVLO
V
DD_OK
IN
2
OUT (FAN3121)
7
OUT (FAN3122)
100k
Non-Inverting
100k
(FAN3122)
V
DD
100k
6
OUT (FAN3121)
OUT (FAN3122)
EN
3
5
GND
GND
4
Figure 7.
Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
www.fairchildsemi.com
4
FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
V
DD
V
EN
V
IN
V
OUT
T
L
T
J
T
STG
ESD
V
DD
to GND
EN to GND
IN to GND
OUT to GND
Parameter
Min.
-0.3
Max.
20.0
Unit
V
V
V
V
ºC
ºC
ºC
kV
GND - 0.3 V
DD
+ 0.3
GND - 0.3 V
DD
+ 0.3
GND - 0.3 V
DD
+ 0.3
+260
-55
-65
Human Body Model, JEDEC JESD22-A114
Charged Device Model, JEDEC JESD22-C101
2
1
+150
+150
Lead Soldering Temperature (10 Seconds)
Junction Temperature
Storage Temperature
Electrostatic Discharge
Protection Level
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
DD
V
EN
V
IN
T
A
Supply Voltage Range
Enable Voltage EN
Input Voltage IN
Parameter
Min.
4.5
0
0
-40
Max.
18.0
V
DD
V
DD
+125
Unit
V
V
V
ºC
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
www.fairchildsemi.com
5
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